well this chip has undergone some revision, there is now a 64MHz version I believe. I would assume that the CPU running at a lower voltage on the same silicon can only achieve a certain speed. But if a mere 6% more clock were to tip the TCC input over the edge I would doubt anything over 48MHz, as we already know the CPU is now rated for 64MHz, I don't know if it is due to a change in process that has allowed this but with the DPLL capable in theory of going higher, I'm sure I saw a spec somewhere in excess of 100MHz the mere 4 MHz between two peripherals designed to work at nearly 100MHz would have me doubting the entire thing.
I have run the TCC from 96MHz with no issue but of course this is at room temperature and like my experiments about 3 years ago on this chip you can even get away with one less wait state than you should at room temperature but of course not advisable in real life. Given this I would doubt that the TCC input is that marginal to have been dropped from 96 to 92MHz.
Now the ADC has a maximum frequency of 16MHz, at this frequency it will do the rated 1MSPS with the default 4 clock periods of sampling time. The minimum prescaler of the ADC is 2, so if I were to use 48MHz I would have to divide it by 4 as 24MHz is too fast, that would run it at 12MHz or 750kSPS.
The prescaler is 2 or 4 or a higher power of 2, 32MHz is the minimum frequency required to get the 16MHz, but 32 MHz cannot be obtained from anywhere but the PLL.
The SAMC seems to be a bit of an unappreciated gem, my apprentice eventually admitted once I got him to read the datasheet that it is a cool chip and he is an STM32 fan, I mean a micro that can run the CPU at 48MHz and have a 96MHz clock all from a RTC crystal, that STM32 garbage would require you to have a second crystal or you would have to contend with the RC clock. Whoever designed the SAMC thought of just about everything. It's just a pity that they did not make more effort with documentation.