I remember a discussion we had on RISC-V regarding carry flags and how they were a pain to deal with, in particular for instruction dependency in a pipeline.
I wrote something recently about the three steps needed to compare two variables and branch based on that, and five different ways various ISAs split those steps up into different instructions and communicate between those different instructions.
It's at ...
https://www.reddit.com/r/embedded/comments/uihmry/comment/i7dpc4h... but I'll copy it here. The initial reference point was PIC.
-------
One further example: there are no conditional branch instructions but instead conditional skips, so to conditionally branch you skip one instruction and goto !
That's a lot less weird than having the awful memory paging only because they were too cheap to put a wide adder in the address generation.
Many ISAs have quite limited range on their conditional branch instructions -- often just 8 bit range i.e. ±128 bytes (or instructions). Some only have 3 or 5 bit branch offsets. If that's far enough then great. If it's not then you reverse the condition and branch over a jump. With the very short fixed length instructions in PIC (just 12 bits in some models, 14 in many more) they don't have room to encode a branch offset along with the 5 or 7 bit register number and 3 bits for the bit to test, and 1 bit for whether to branch on clear or set.
Doing a conditional branch based on two variables has three parts to it:
1) subtracting the two values,
2) deciding if the relationship you want to test (eq, ne, lt, ge) is true or false, and
3) branching to the destination if the test succeeds.
RISC-V with fixed size 32 bit instructions does all this in one instruction:
blt r12,r13,.+345 // ±4 KB range
In PIC this needs four instructions (unlike the other examples, this is unsigned, signed is harder on baseline/PIC12/PIC16 with only C and Z flags, N was added in PIC18)...
movf 13,1
subwf 12,w
btfsc 3,0 // C is bit 0 of register 3
goto 345 // relative addressing not supported
Probably the largest number of ISAs combine the first two instructions into a cmp (sub that doesn't write the result anywhere) that sets a multi bit flags register, then combine the test of which condition is desired (eq, ne, lt, ge, and others) and the branch into a single instruction:
cmp r12,r13
blt .+345
But a few use a general register to store a 1 or 0, and combine the subtract and the comparison type in one instruction, then branch simply on true/false. e.g. MIPS
slt r8,r12,r13
bne r8,.+345
Another variation is to have a kind of condition code register but have only one bit, which functions the same as r8 in the above MIPS code. e.g. SuperH
cmp/ge r13,r12 // result stored in T bit
bt .+345 // branch if T bit is True