Regarding the reference Voltage, I've noticed with a number of OCXOs it is set to rather less than the total tunining range (e.g. around 7V or so when the range is up to 10V). In this case the 5.1V (or 5.09V to be more precise) seems to be roughly twice the initial tuning voltage for 10MHz (based on what I measured on my not very precise counter on my oscilloscope).
I would have thought that dual power supplies (12V and say 5V or 3.3V) wouldn't be too much of a problem as the 5V parts are presumably very low current compared with the OCXO so a simple linear regulator chip with a couple of capacitors would be ok and doesn't add much to the number of components.
I admire your tenacity in working with the 13MHz part. I have a number of 13MHz OCXOs some of which are quite good but if I was to use them in a GPSDO I'd probably make it a 1MHz one (divide by 13) or perhaps have a second PLL with a 10MHz crystal.
The 13MHz parts are all from GSM systems I think where it is an exact multiple of the bit rate (according to Wikipedia). I wondered if it was possible to try locking onto a GSM signal but I suspect that idea is a non-starter (having got these 13MHz OCXOs because they were cheap I am now hunting around for applications!)
'Scope based frequency counters leave a lot to be desired, even the 6 digit hardware ones as used in the SDS1202X-E I bought just over six months ago (that read 30Hz high to begin with but now seems to be within 10Hz of actual, presumably due to the XO reference having now aged itself closer to its design frequency).
Since I've upgraded the cheap 'Ten a Penny' smd xo chip used by Feeltech in their otherwise excellent, penny pinching cost cutting deficiencies aside, FY6600 to a 10MHz OCXO with 3N502 clock multiplier to improve the original 50MHz reference by a good five orders of magnitude of accuracy and six orders of magnitude of stability, the 'scope counter is now merely a useful sanity check that the signal it's locked onto is in the
right ball park (never mind '
the ball park' - I've been chasing down measurements in the ppt range for the past month now - ppb accuracies are now just a memory of my earlier ambitions).
It's true that providing stable regulated DC voltages in a multi-rail setup is now routine thanks to LDOs of various types, the big problem when it comes to frequency stability measured in ppt, is that the once insignificant voltage changes on these rails due to variations in loading can no longer be tolerated when it comes to OCXO tuning voltages. The classic way to obviate this is simply to use a separate regulator dedicated to only this function, preferably one that is itself powered from another regulator at a voltage between the relatively unstable supply (12v to 9v LDO feeding a 5 or 3.3 volt LDO or even a separate mains to 12vdc smpsu feeding a 9v then 5v with possibly even a 3.3v LDO hung off the end of that chain.
The OCXO manufacturers are obviously aware of this demanding requirement so will typically offer the internal LDO's output on a Vref pin (it only has to supply some 10 to 15mA at most to the constant load from the XO itself - I've noticed the undershoot of the heater current during initial warm up dropping to a steady 14mA minimum before the temperature control turns the heater transistor current back on in both the 5 and 12 volt CQE OCXOs - as I mentioned earlier, this is one of the insights I gained into the inner workings of these CQE OCXOs
).
In most cases, this can be used directly to feed a 50K trimming pot or a cmos RRO opamp/dac arrangement, free of the millivolt variations of the general 5 or 3.3 volt supply rail. Failing that (the voltage isn't high enough for example) it can be used as an amplified reference voltage with another suitable cmos RRO opamp to create a higher tuning voltage supply with a stability matching that of the OCXO's internal oscillator supply voltage. As you said, it's only a minor complication to provide a separate dedicated tuning voltage supply, free of the effects from the rest of the GPSDO's loading on the main power supply rail.
Thanks for noting my 'tenacity' with recreating a
functioning divide by 13 circuit out of a '193 IC.
Putting aside my oversight of the need to ground the clear input pin, it's not difficult to convert the 13MHz into a 1 or 10 MHz sq wave frequency reference (the 10MHz option requires at least one 3N502 multiply by five chip and a frequency doubler to make sure it gets a 2MHz input (the 3N502 isn't specced for input clocks below 2MHz - I used another '502 to double up the 13MHz before feeding the divide by 13 circuit to meet this 2MHz requirement but a simple RC delayed input XOR gate frequency doubler would have done the job, saving that extra '502 for more productive use elsewhere). I wouldn't be quite so quick to discount those cheap 13MHz OCXOs as a substitute for a 10MHz reference oscillator if I were in your position, unless you've got a surfeit of 10MHz OCXOs to hand of course.
In the end, I stripped the '502s out of the circuit leaving just the '193 to convert the 13MHz into a 1MHz signal which I then fed into one and a half '390s to feed a simple '86 based PD with the required 1KHz to lock to the NEO-6M's 1KHz output from its PPS line. At this stage of the game, any "reference frequency output" will do for my current purpose - I'm just trying to get a functioning PLL circuit proven. Even with this chip count reduction, it was still a tight fit on my prototyping breadboard but I was able to get results of a sort. I rather suspect I might be needing an inverting buffer amplifier between the output from the RC filtered PD output and the tuning control pin on the OCXO.
As it happens, the ten 5v cmos RRO opamps I'd ordered from a Chinaman about a month back did finally turn up last week but I need to mount one on a SOT to DIP adapter board before I can add it to my breadboard lashup. In the meantime, I did try cheating a solution to this suspected requirement by using a spare XOR gate as an instant phase reverser for one of the PD's inputs (clutching at straws rearguard action on my part) by feeding one of the input signals into an input pin of a spare gate in the '86 IC and grounding the other input to change it from a logic high (internal pullup) to a logic low as an easy and convenient means to effect instant phase reversals at will. Needless to say, it didn't really make a useful difference in spite of it producing an immediate (and initially promising) effect.
When it had seemingly 'locked up', I could see that the GPS was doing something useful by disconnecting the antenna which then caused the frequency to drift rapidly from the target frequency when satellite lock had been lost, followed by a rapid shift back onto frequency when lock was regained after reconnecting the antenna. The PD circuit was obviously doing
something but it had a tendency to slip inexorably out of lock, first to the high side then to the low side over periods of 10 to 15 minutes.
I'm not entirely sure what the problem is. I have many theories and contenders by way of poor component choice(s) to play around with. It's basically a negative feedback setup so one might think there'd be a lot of latitude in component value selection. However, I'm aware of the issue of 'phase stability' in such negative feedback loops turning them into positive feedback loops at critical frequencies when the gain can equal or exceed unity. Creating stable negative feedback networks can prove more difficult to achieve than it appears on the face of it and I obviously need to study this problem some more.
One possibility is that the rather ancient, original TTL 7486 XOR gate I'm using isn't really suited to this PD circuit but it was the only '86 I could find in my four decades old collection to test with. I've got a five piece set of the more modern 74HC86s headed towards these shores on the slow boat from China at just 99p the lot (as opposed to the silly money being asked per single IC by the greedy, profiteering UK dealers - I'd hoped my single 7486 chip would save me the indignity of going to one of these UK dealers, begging bowl in hand - it may do so even yet, given enough lateral thinking).
Of course, there's also the effect of the jumper styled wiring used on such prototyping breadboards, along with the less than reliable contact performance and the problems of arranging for effective high frequency bypassing of the supply voltage feeds to the ICs used to contend with. Then, in this case, comes the issue of the quality of the 220, 22 and 1 microfarad Al electrolytics I used (taken from a PD circuit from off the web), any one of which could be contributing excessive leakage effects.
Reassembling with the original components, Manhatten 'dead bug' style on a piece of groundplane PCB might instantly cure the prototyping breadboard issues but, since the high frequency digital processing circuitry seems to have survived such indiscretions of construction and I'm now dealing with a mere 1KHz (admittedly sq wave) signal, I'm not so sure such an improvement in the reduction of high resistance connections and unwanted lead inductances would do much for the PD circuit in this case.
However, I do recall the time when I was 'breadboarding' my design of a 200W RMS per 4 ohm loaded channel bridged output PA design some 50 years back onto tag board, soldered connections al fresco layout (better than the current prototyping breadboard setup) and experiencing strange instability issues which had me convinced that the only way to properly test it out would be to commit it to a PCB (hand drawn and etched with ferric chloride in my workshop) which conclusion turned out to be correct, so there may yet be some mileage in going this route after all, as unlikely as that would appear.
BTW, my 'phase lock loop' appears to have stabilised (I powered it all back up about an hour ago) but at a 100mHz offset from the FY6600's 13MHz setting. There's a slow but quite discernible drift with the control voltage sat at 3.26v at the moment (it can swing, for no apparent reason, between some 2 and 4 volts). I know that the drift should be a barely discernible 10mHz or so when 'locked' which makes the resulting "locked" state, quite frankly, rather inexplicable.
I know this isn't the locked state because if I trigger directly from the PPS output, the 13MHz Sinc pulse waveform takes some 5 to 10 minutes to slip one full cycle rather than the ten seconds or so that it's doing right now.
Never mind, it's a result of sorts... I've just noticed it was starting another trip to the high frequency end of its range (I've now got a 50K pot wired to the tuning control line to limit the extreme excursions in the hope it would lend some stability - it helps a little but it doesn't cure this 'locked to not exactly the correct frequency' syndrome). I disconnected the antenna to force loss of satellite lock and, sure enough, when this happens it suddenly jumps up in frequency and then drops back onto its 100mHz above frequency 'lock' state when satellite lock is regained.
To my mind this "almost works properly" is a really weird effect, I would have expected it to either work or else keep dancing from one extreme to the other without any pause close to the desired frequency. I wasn't expecting this sort of behaviour from this circuit so it's quite a conundrum.
JBG
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