Buffer for Kelvin Varley Divider

[WillTurner]

Just a reminder that Jim Williams (et al.) discussed buffer circuits extensively in Appendix C ("Verifying Data Converter Linearity to 1ppm") of AN-86 ("A Standards Labs Grade 20-Bit DAC with0.1ppm/C Drift" January 2001). Starting with an LTC1152/LT1010 op amp and driver, he adds some simple trim and monitoring  .

[3roomlab]

Near to black magic 

An ideal junction itself cannot generate t-emf.
A "junction"/jumper as shown can only generate t-emf when there is a temperature difference between both ends.

The principle of the  Seebeck effect is described in detail e.g. on Wikipedia.
Bit of black magic is revealed in Keithleys Low level measurement Handbook p. 116.

yes black magic like harry potters poop !
harry potter must be good friends with TI / microchip
I found 2 of their poops, now everyone can smell it and cast magic spells (hopefully)
the description of thermal emf across the smd is really good read.
and the microchip section on leakage resistance, I think you could literally count Gohm squares to estimate leakage

[Crossphased]

This is the schematic of my buffer. I needed to brush it up a little to match the new symbols in KiCAD 5.1. I will need to update the PCB as well, then I will put it all on Github. Probably tomorrow or so.



The idea is, that the zener diodes will bias the op amp supply around the output voltage. The supply will always be about 6.2 V - 0.7 V (one diode drop due to the transistors) = 5.5 V above and below the output. This ensures good performance of the op amp, which is spec'ed at +-5V.  This will require +- 18V supply rails to make sure we will not rail at 10 V (10 V + 6.2 V = 16.2V). The bootstraping has two positve side effects. For one, it increases the output voltage range. Second it increases the CMRR which would otherwise introduce an error. Since the the minimum of the op amp is 120 dB (1 ppm), this would degrade the Fluke 720A. In this design it is not neccessary to check the op amp. The common mode voltage stays the same throughout the whole range. You might want to select the op amp for input bias current though.

The PCB I did fits into one of those RND aluminum enclosures: https://www.distrelec.de/en/metal-enclosure-64x58x35mm-aluminium-alloy-ip65-rnd-components-rnd-455-00367/p/30064588 . I will post some pictures later.

Awesome thanks very much for this maat!!

[Crossphased]

I've got a quick question about protection for the buffer. In the past I've been known to absent mindedly  connect things to pieces of equipment before applying power to the unit. I've tried to make it a point to put some kind of protection to guard against my forgetfulness. Would it be appropriate to put something like ADG1221 or ADG5419 on the input to protect against this sort of thing? Perhaps "bootstrapping" the digital input to the same level as guard voltage, so signal cant leak? Or would there be a better method to protect the opamp from voltages applied when its off?
Cheers!

[Crossphased]

Something like this:

[maat]

I've got a quick question about protection for the buffer. In the past I've been known to absent mindedly  connect things to pieces of equipment before applying power to the unit. I've tried to make it a point to put some kind of protection to guard against my forgetfulness. Would it be appropriate to put something like ADG1221 or ADG5419 on the input to protect against this sort of thing? Perhaps "bootstrapping" the digital input to the same level as guard voltage, so signal cant leak? Or would there be a better method to protect the opamp from voltages applied when its off?
Cheers!

I absolutely recommend against any analog switch. Usually they bring more problems to the table than they solve. Unless you need to switch something really fast or really often. You *could* use a bistable relay, but I would say put 1k in series and you should be fine up to 10 V (low impedance). Given that you connect the buffer to a KVD they output impedance of the divider is large enough to apply any sensible voltage to the divider and not harm the buffer.

If you are utterly paranoid put in the 1k and and a BAV199 to both rails (or two 2N3904, shorting B-C, one to each rail) behind the resistor at the expense of additional leakage. But that is overkill in my oppinion.

[maginnovision]

The switch also adds another 10-40pA leakage. Maybe try the simplest version and double check your setup. If it works and you're happy then you modify.

[Kleinstein]

A series resistor and maybe a series inductor (may help with short pulses like ESD and maybe RF interference) is already a good first protection.

For input current protection one could mimic the protection inside chips like the DG508:
2 JFETs with a resistor in between can be used as an effective bidirectional current limit. One may even get them as current limiting diode (though rare and thus likely expensive). For higher voltage (up to some 600 V) one could use depletion mode JFETs like BSP135).

The diodes (e.g. BAV199) could be bootstrapped from the output to reduce the voltage over the diodes to near zero. A small capacitor to ground can also help to catch some ESD and also reduce EMI (in both directions). With AZ OP is may be a good idea to have some filtering at the input, as there are some RF signals coming out and the returned RF could effect the bias and maybe offset.

[MiDi]

With AZ OP is may be a good idea to have some filtering at the input, as there are some RF signals coming out and the returned RF could effect the bias and maybe offset.

Not only for RF, the charge injection to inputs of AZ OP from itself can affect offset-voltage.
A low enough input impedance at chopping frequency is needed to get low offset-voltage.

I learned yesterday that the choppers need a low impedance at their input pins. The OPA189 with 100k to the non inverting input had a 650uV offset. With a 20pf or 2000pF COG cap to ground the offset was less than 0.2uV. Other op amps like the LTC2058 and he ADA4522 need the full 2000pF to get below 1uV. I don't know yet if higher capacitance helps them more.

[razvan784]

I don't think you need a guard trace around the inverting opamp input, because that is relatively low impedance - it would needlessly complicate the layout. You absolutely need one around the + input though.
Re: protection, maybe a low voltage GDT right at the input, followed by a resistor to limit the current to whatever the opamp protection diodes can tolerate. Note that the LTC1052 lacks such a specification, unlike more modern opamps. It even warns you to never exceed the supply voltages or risk "destructive latchup". As I understand the wording in the datasheet, protection diodes (internal or external) are not enough to prevent this.

[Andreas]

This is the schematic of my buffer.

Hello

is C9 + C10 really connected to common ground?
All cirquits that I have seen connect the capacitors to pin 4 of the LTC1052

with best regards

Andreas

[maat]

This is the schematic of my buffer.

Hello

is C9 + C10 really connected to common ground?
All cirquits that I have seen connect the capacitors to pin 4 of the LTC1052

with best regards

Andreas

Oh yes, indeed 
This was a remnant of an older verison, I used to buffer a DAC, that did not go to GND. Thanks a lot for pointing it out. I fixed my other post.

[Crossphased]

A series resistor and maybe a series inductor (may help with short pulses like ESD and maybe RF interference) is already a good first protection.

For input current protection one could mimic the protection inside chips like the DG508:
2 JFETs with a resistor in between can be used as an effective bidirectional current limit. One may even get them as current limiting diode (though rare and thus likely expensive). For higher voltage (up to some 600 V) one could use depletion mode JFETs like BSP135).

The diodes (e.g. BAV199) could be bootstrapped from the output to reduce the voltage over the diodes to near zero. A small capacitor to ground can also help to catch some ESD and also reduce EMI (in both directions). With AZ OP is may be a good idea to have some filtering at the input, as there are some RF signals coming out and the returned RF could effect the bias and maybe offset.

Thank you Kleinstein!

Is this in accord with what you had in mind? Are these part values appropriate?

[Kleinstein]

The mmbf4393 is a possible choice. Other types are also possible, like mmbfJ201. The resistor may need to be a little larger for a lower current.
A 10 nF capacitor looks rather large to me. I would more expect some 100-500 pF, with possibly a 2nd cap from before the fets.
Depending on the inductor type used, it may want a parallel resistor for dampening.

There are still not diodes to sink any current exceeding the supply of the OP, so the current limiting is of limited value unless the current is set very low, to a level the LTC1052 can tolerate.

[Crossphased]

The mmbf4393 is a possible choice. Other types are also possible, like mmbfJ201. The resistor may need to be a little larger for a lower current.
A 10 nF capacitor looks rather large to me. I would more expect some 100-500 pF, with possibly a 2nd cap from before the fets.
Depending on the inductor type used, it may want a parallel resistor for dampening.

There are still not diodes to sink any current exceeding the supply of the OP, so the current limiting is of limited value unless the current is set very low, to a level the LTC1052 can tolerate.

Thanks very much for your feedback Kleinstein, very much appreciated. How does this look-

[Kleinstein]

The BAV99 is not really low leakage - the low leakage (but high forward voltage) diode type is BAV199. Ideally one would have diodes in both directions, like 2 BAV first and than bootstrapped followed by BAV99 to the supplies (or lower).

The JFET part mainly makes sense with a diode behind. Without the diodes the current would likely need to be set much lower (e.g. 10 to 50 K resistor).

[Crossphased]

The BAV99 is not really low leakage - the low leakage (but high forward voltage) diode type is BAV199. Ideally one would have diodes in both directions, like 2 BAV first and than bootstrapped followed by BAV99 to the supplies (or lower).

The JFET part mainly makes sense with a diode behind. Without the diodes the current would likely need to be set much lower (e.g. 10 to 50 K resistor).

Got it. Just going to increase the resistor size to 20K. Did the math and for every pA of bias current, the 20K only drops 20nV. So even at 10pA bias, thats only 200 nV so that sounds good to me!



For the BAV199 alternative, is this what you were thinking of with diodes to both rails?


I think it will be easier to guard the input better with just the jfets and not the BAV199

[3roomlab]

I ran 2 simulations out of curiosity
both using 100pf 2kv/8kv model @ 500R (not 1.5kohm)
the ESD is precharged @ C17 and released by S1

the first is jfet fronted (note IPP to IP2 path J1/J2)
the 2nd is just 2 stages of 500pf
before this, I had tried w/o TVS, the surge appears to be too great w/o TVS
the 2 stage 500pf seem to work better (simulation wise). the 2 stage caps appear to have 4x less surge seen by the opamp.
one depends on current limiting, the other depends on current absorption.

for those who wish to try, the TVS lib/txt is attached
(as you can see the mess, I tried a few TVS models from diff mfr. every model have different response)

[Crossphased]

I ran 2 simulations out of curiosity
both using 100pf 2kv/8kv model @ 500R (not 1.5kohm)
the ESD is precharged @ C17 and released by S1

the first is jfet fronted (note IPP to IP2 path J1/J2)
the 2nd is just 2 stages of 500pf
before this, I had tried w/o TVS, the surge appears to be too great w/o TVS
the 2 stage 500pf seem to work better (simulation wise). the 2 stage caps appear to have 4x less surge seen by the opamp.
one depends on current limiting, the other depends on current absorption.

for those who wish to try, the TVS lib/txt is attached
(as you can see the mess, I tried a few TVS models from diff mfr. every model have different response)

Interesting,
I'm going to try the sim myself. I'm not as worried about ESD, more concerned about 10-15V applied to the input with no power to opamp. I have a question- what is the purpose of putting C12+19, C20+C21 in Series? Increase voltage capacity?  Also I'm going to try simulation with jfet current limiting & 2 stage caps instead of no caps for the jfet current limiting. Also how come only 26nH for the choke?
Thank you very much for posting the simulation it is very kind and helpful of you

[3roomlab]

the 68n is modelled with 440G leakage resistance. I wanted to see how bad is leakage effects. vs C0G
I left many idle components around in the picture, so some/most are remnants of simulation versions 

[splin]

I would use an OPA140 rather than the LTC1052 for several reasons:

1) 0.1 to 10 Hz noise              250nVpp v 1500nVpp
    .1 to 1Hz noise (estimated)  140nVpp  v 500nV

2) Ibias max (typ) @ 25C  10pA (.5pA) v 30pA (1pA)

3) Cost.   (1 off) $3.29 v $8 to $10 + capacitors + protection

4) I/p protection - easy v tricky(er)

5) No charge injection Ibias noise/artifacts which could disturb other connected instruments.

The disadvantages:

a) Offset voltage drift with temperature - 1uV/C (.35uV typ) v 50nV/C (10nV/K typ).

b) Ibias for temperatures above 35C (doubles with each 10C rise).

c) Avol min (typ) 120dB (126dB) v 120dB (150dB)

CMRR is similar for both at 120dB. Avol and CMRR min for both amps is too low to be used without bootstrapping.

Voffset is not as good for the OPA140 but you will have to zero out any measurements anyway as the LTC1052's maximum offset is 5uV which is too high. Zeroing is also required to remove thermal EMFs which will be a problem for sub-ppm measurements.

I would expect the thermal EMFs to vary as much with temperature as the OPA140's drift so if your environment is not sufficiently stable you will need to re-zero periodically whichever buffer amp you use. That should be quite easy unless you are running long term automated measurements.

Ibias could be a problem for both amps but especially the LTC1052 - selecting amps for low Ibias is not likely to be affordable at $8+ a pop. Bias compensation may well be required, but straightforward if the buffer is bootstrapped. Either way it does mean having to measure the bias current (easy enough with a capacitor).