Using an ADC as an RF power detector and DDC/FFT resolution?

[Andrew_K]

Hey All,

I am trying to measure the power of a single frequency tone which varies by a small amount over time.

Currently my design uses a logarithmic RF detector, but it is rather wide-bandwidth and I'm running into issues with noise and interference being picked up... I'm considering using a direct sampled architecture to reduce cost, and hopefully allow better DSP filtering.

Now what I am struggling to figure out is the resolution I might get. I know that with decimation, every factor of 4 effectively gives me a new bit, or 6dB of SNR. But what if I use something like an FFT or a digital-down-conversion?

I feel like I must get better resolution/SNR with an FFT because I am paying attention to a particular frequency bin. I tried playing with this concept in GNU radio. It seems like I get significantly better resolution with the FFT method, certainly more than 1 bit per x4 decimation.

I can't seem to find any equations or resources on this topic, so maybe I am using the wrong terms in my searches...
I would really appreciate some more information, or if anyone has a book or resource they would recommend?

[gf]

Which frequency? Which power level?
What varies over time? Frequency or power?
Do you know the frequencies and power of the interferers? Or is it just broadband noise? Did you measure with a spectrum analyzer?
Particularly if you want to do direct RF sampling (bandpass samping) then you need to come up with a suitable frequency plan which enables separation of desired and undesired frequencies. Even if a suitable frequency plan can be established, you still may need pre-selection filters if the power of the interferers is too large.

Processing gain is just a matter of bandwidth. The basic idea is, if you reduce the measurement bandwidth, then a smaller amount of broadband noise power falls into the measurement bandwidth. The narrower the bandwidth of the detector, the less broadband noise power is captured. At the end it does not matter how you do the filtering (note that FFT can also be considered a filter bank). A selective single-frequency detector can be easily realized via "single-bin DFT", i.e. you don't calculate the full FFT, but you calculate the DFT only for a single frequency. Goertzel algorithm does basically the same, but recursively with an IIR filter. If rejection of interferers is important (and not just reduction of broadband noise), then a window function with a high selectivity and stop band rejection can be used with the DFT.

[EC8010]

As you've spotted, you can improve S/N (but not linearity) by decimation. Amplitude of white noise is proportional to the square root of bandwidth, so reducing bandwidth reduces noise under your wanted signal. As pointed out, it doesn't matter where that filtering occurs. You've mentioned FFT, and another technique is lock-in (might be a useful search term). Both rely on the ADC or multiplier being linear and not being overloaded by noise or interference. Although you can achieve very narrow bins with a long record length and FFT, if your frequency of interest drifts, it will spread across bins. It's still possible to calculate its amplitude, but you now need to estimate and subtract the noise power underneath it, which you can do by measuring noise power per bin either side of the region of interest. But your uncertainties will increase. As with many problems, it's best not to try to use one single technique to achieve all the improvement you need, rather a combination that adds up. Thus, I would use a resonant LC filter centred on the frequency of interest to broadly reject noise/interference, then an ADC and FFT. If your frequency of interest is RF and stable, you might need a GPS-locked reference for your sampling ADC.

[Andrew_K]

The RF tone will be referenced to the same clock my ADC will use. Should be pretty stable. Good insight on using more than one method. Definitely will plan to do that.

I guess I'm still a bit confused on what the smallest power level change that could be measured. Would I want to use # of bits and decimation like for voltage?

For example sake, let's say it's a 10 bit ADC, FS = +/-1V = 10dBm, 50ohm input, and can decimate by a factor of up to 256x (4bit).

With averaging I can get 14 bits in terms of voltage counts. Smallest change in voltage I could measure is 2/2^14 or about 122μV. But how about power levels? Would that be 10mW/2^14 = 610μw? Or do I get more out of it?

I guess I'm looking for the equations to calculate minimum power change detectable.

[EC8010]

You almost certainly don't genuinely measure power. You measure voltage, then convert it to dBm or whatever. Unless, of course you use a thermocouple meter, in which case you genuinely do measure power. So... Probably best to think about it in voltage terms. Without knowing what it is you're measuring, it's hard to guess what would be appropriate. In general, measuring AC to better than 0.1dB is tricky. 0.01dB is pretty well the practical limit. Yet my oscilloscope reports to thousandths of a dB! Amplitude resolution is limited by the resolution of your ADC and by noise. Oversampling/decimation can help. If you have a 'scope that allows you to oversample (high resolution mode) it will reduce noise. Some 'scopes don't merely oversample but invoke defined low-pass filters as their decimation. A Tek 5 Series employs a 36dB/octave Bessel filter as its high resolution decimation. If you genuinely have a clock referenced to the signal you're looking for, you can afford to use a long record length an narrow frequency bins, minimising noise. If you have 14 bits, you have a theoretical S/N of 6n dB or 6 x 14 = 84dB. But that assumes a noiseless ADC and front end. But it's a reasonable starting point. But what are you looking for? A tiny signal buried in noise or very small amplitude changes in a large signal? Beware that with all these averaging tricks, you might easily filter away the very changes you're looking for. You really need to define your problem.

[langwadt]

FFT is similar to DDC jsut at many frequencies, mix with complex sine and low pass

[Andrew_K]

It's basically a rather large signal with small changes in amplitude. In power, let's say it could vary by 0.005dBm over a second. Using a "16 bit" ADC with the datasheet saying the SNR makes it about 14.5 bits. Sampling rate let's say 100MSPS.
Could I use a higher bit ADC like a sigma-delta? Normally this would be ideal, but there's impulse noise that I can't simply low-pass filter out.

I think decimation is definitely on my side.

You're right, the ADC is measuring voltage (across the known impedance), so power is calculated. So, it is still a voltage I am measuring. So that must mean that the SNR/bits limit still holds?

But I must get better SNR when I use FFT/DDC because of the effective filtering?

[EC8010]

Yes, FFT/DDC helps reduce noise. However, those expected statistical gains assume an ideal ADC or DAC whose performance is perfectly described by its bit depth. Semiconductor manufacturers like to specify integral non-linearity (INL) of converters because it's usually quite good. When they specify that a converter is monotonic, they mean that a linear rising ramp applied to the input of an ADC will always cause the output to count up - never down. But what that means is that it is perfectly possible to have two adjacent quantising steps where one step is 1/2LSB and the other is 3/2LSB. That's going to cause you problems. It's defined in data sheets as differential nonlinearity (DNL). However... If you know the phase of the signal you want to measure, you don't need to measure each and every point of the sine wave, you just need to measure a few points around the peaks (perhaps ten either side). And if you know the expected amplitude, you now only need a low resolution ADC measuring offset from those expected amplitudes. That should be much easier.

If you only measure twenty points or so at each peak, you could curve fit a sine wave through them, and that would effectively give you a low-pass filter to reduce noise. You could even drive a DAC to produce the curve fitting point and adjust for minimum measured noise (difference between DAC output and measurand).

[langwadt]

It's basically a rather large signal with small changes in amplitude. In power, let's say it could vary by 0.005dBm over a second. Using a "16 bit" ADC with the datasheet saying the SNR makes it about 14.5 bits. Sampling rate let's say 100MSPS.
Could I use a higher bit ADC like a sigma-delta? Normally this would be ideal, but there's impulse noise that I can't simply low-pass filter out.

I think decimation is definitely on my side.

You're right, the ADC is measuring voltage (across the known impedance), so power is calculated. So, it is still a voltage I am measuring. So that must mean that the SNR/bits limit still holds?

But I must get better SNR when I use FFT/DDC because of the effective filtering?

if you are also generating the tone than you already have the signal to mix your signal down to DC, then you you can lowpass/average as much as you like with in the limit of how fast changes in level you want to see

[gf]

It's basically a rather large signal with small changes in amplitude. In power, let's say it could vary by 0.005dBm over a second.

Do you mean 0.005 dB (not dBm)? Is your goal just discriminability? Or in other words, if you get two readings of 1.0V and 1.000576V, is your aim to have high statistical confidence that the true amplitude of the 2nd one is really larger than the true amplitude of the first one? If you want (say) five sigma confidence on each side, so that the overlap of the two PDFs is really just marginal, this implies that the standard error of the measured magnitude must be < 0.000058 times the magnitude. A DFT-based detector with rectangular window and N points requires the input signal to have a SNR of about >= 85dBc - 10*log10(N) to achieve this goal. E.g. for N=100000, the a priori SNR of the signal fed into the detector must exceed 35 dBc.

[ This consideration assumes Gaussian random noise. If your noise PDF is different, or your noise is not white, you'll get different numbers. Any systematic (non-random) interferences need to be analyzed and considered separately. So the point is: You need enough a priori knowledge about the signal you are dealing with, and about included noise and interferences, in order to predict the outcome. ]

Using a "16 bit" ADC with the datasheet saying the SNR makes it about 14.5 bits. Sampling rate let's say 100MSPS.
Could I use a higher bit ADC like a sigma-delta? Normally this would be ideal,

14.5 bits is 89dB_FS. But that's just the contribution of the ADC alone. But it becomes negligible if the noise level which is a priori present in your signal happens to be much higher. If the a priori noise level is large, then even a 12-bit ADC may not make a significant difference at the end, compared to 16-bit. Note that random noise dithers the ADC, which also improves its DNL.

but there's impulse noise that I can't simply low-pass filter out.

You really need to qualify and quantify the non-random noise components polluting your signal, in order to find out whether they can be separated from the useful signal at all, and if yes, to get an idea how it could be done.

Can't you feed your signal into a spectrum analyzer, or into a scope with large FFT (if the frequency is not too high) to get at least a first idea?