Seems appropriate to bring up a question I had recently. I've been using some low melting solder, tin/bismuth/silver, and wondered if anybody knew how it performed for thermal emf against copper? Turns out it's pretty common stuff and can be had from Digikey. Brittle and not great conductivity, but seems to flow well and works like, well... solder.
I found the value at one point, and don't remember it exactly, but it is worse than lead free solder. I want to say around 6 uV/K, but I am sure someone with the value at hand will fact check that.
Regarding the OP, you bury the lede a bit here - the identical values using two solders with Seebeck coefficients you have characterized in the experiment seems to suggest that the observed effects are attributable to the resistors alone. In my first comment, I didn't really understand how the connections were made, but it's obvious that the amplifier is on the board, so I withdraw that objection. I still am not 100% clear on this though. It would be helpful if you could show the whole board layout. Also, I can't tell this to a certainty by looking at the picture, but it looks like you have a ground plane on the bottom based on color. Is this the case? Could you comment on the layer count and stackup?
I am not saying you should make another board, but I would think the ideal design of the board would be one where one prioritizes having a predictable thermal gradient. I would use a four layer board with ground planes on three layers and thermal vias. At the ends where you are applying or removing heat, it would be good have a lot of thermal vias and large areas where the solder mask is removed so you can solder heat pipes onto both sides of the board perpendicular to the intended thermal gradient axis. This would seem to do the most to ensure the temperature differential between two points of the board is easy to characterize from position alone. This experimental setup is certainly capable of showing the impact of solder, but with significant uncertainties around the nature of the thermal gradient, it becomes somewhat difficult to apply these results to layout.
Having just laid out a nanovoltmeter, I'll give the considerations I weighed as they may suggest avenues of experimentation:
-placement of things that dissipate power to minimize thermal gradients at sensitive nodes. I would have liked to use FIE to simulate different designs, but I don't have access to such tools so I listed out the largest dissipators using envelope calculations or SPICE simulation and placed things that dissipated approximately equal amounts of power on opposite sides of sensitive nodes.
-Routing key differential signals next to each other and placing junctions symmetrically about the axis of (assumed) temperature gradient
-Using 0402 resistors and no-lead packages (DFN, QFN, etc.) where feasible for minimizing space between sensitive junctions.
-Balancing the size of traces at the ends of discrete resistor dividers and orienting them perpendicular to my best guess of the direction of thermal gradients.
-Using minimal lands on the largest dissipators to minimize conducted heat transfer.
It would be interesting to know the impact of different resistor sizes and the amount of padstock in the footprint to see how that changes things. The other question in my head during layout was "how bad will this be if I am wrong about the thermal gradient here," which would suggest experiments where a certain resistor string is oriented at two different angles to a known temperature gradient. That is a crucial issue because different operating conditions (for example, changes in power dissipated along gain-setting resistors) would hopefully have little impact. I would assume that anyone laying out nV-level circuitry has a general familiarity with how to orient things in the ideal case when the temperature gradient is known, but minimizing the impact of uncertainties or forced non-idealities in thermal layout (for example, when trace length needs to be minimized because a node is sensitive to parasitic capacitance) is more difficult. I believe this sort of information would provide the greatest value for anyone laying out low level dc boards. I personally based my design decisions on assumptions from first principles, as well as common design guidelines, but some of those assumptions were probably wrong, and some of those guidelines may not be well grounded. For you to suggest a systematic and quantitative evaluation of this is good science, and I appreciate that you have done the work and are sharing the results. As such, take these suggestions as potential avenues for improvement on what I consider nonetheless to be very positive work. Some things, like substituting resistors could even be implemented with this board.
Also, this isn't criticism because I am sure everyone understands what you are talking about, but for "opposedly" the word you are looking for is "oppositely", and for "meandric", the word is "meandering".