Prema 6048 teardown

[Rax]

So OPA202 arrived yesterday. I gave the unit one night after I've replaced OP77 with OPA202, zero'ed it and measured INL again. Attached the file of the measurement as well as a diagram with the outcome of it.

-branadic-

In trying to close this loop, I think we're replacing the same U9/integrator as before - just a different part this time around than the one tried before - is this correct? Also, U10, though I'm not sure it's been determined which has the instrumental contribution.

OPA140/189 vs. the OPA202 we've looked at before. For all those trying to do this, though, fair warning is calibration will be disturbed.

[Rax]

A change of the OP amps will effect the calibration. The offset of the OP-amps add to the effective 7 V reference voltage. This is not only the offset of the new OP-amps, but the difference to the old ones.
This would be one factor effecting all ranges (including resistance). So there would be a chance to check the scale factor before (e.g. 10 V reference voltage , 10 K resistor) and than at least get an idea on how much change happened.

I think we've already established calibration is thrown off, I was just wondering by how much, I guess. I think you're kind of going that way too. 

[Kleinstein]

So OPA202 arrived yesterday. I gave the unit one night after I've replaced OP77 with OPA202, zero'ed it and measured INL again. Attached the file of the measurement as well as a diagram with the outcome of it.

-branadic-

In trying to close this loop, I think we're replacing the same U9 as before - just a different part this time around than the one tried before - is this correct? Also, U10, though I'm not sure it's been determined which has the instrumental contribution.

OPA140/189 vs. the OPA202 we've looked at before. For all those trying to do this, though, fair warning is calibration will be disturbed.

So yes it is about the same part (U9) as suggested before. U10 is a separate step for a different reason (diodes between the inputs case a spike back to the reference).
The OPA202 is only a little (1 MHz vs 600 kHz) faster than the OP77. This was to avoid possible oscillation with gain in the Prema chip. I consider it bad luck that the resulting INL was still about the same.

With Dieter's discovery of the extra 10 nF capacitor at the OP-amp this is no longer that critical: the OP-amp does the fast part of the integrator and the extra gain is mainly for the slow part. So a much faster OP-amp is possible and should even allow for reducing the 10 nF capacitor. Both the OPA189 and  OPA140 seem to work and chances are neither would contribute significant to the noise.

[dietert1]

When i found that extra capacitor i thought it was a bit large and removed it. Then the integrator was unstable at 1 MHz. so i put a 680pF there. This was still between negative input of the opamp U9 and its output. When i put in the OPA140, i thought a better choice was placing the 680 pF across the amplifier inside the BK7. Now the extra capacitive feedback needed for stability is via the integration cap, but avoiding double integration. To illustrate how the integrator was injecting charge, i have two scope dumps.
First one shows the setup with the op77 and the 120R/10nF filter. Top track is the PWM signal as trigger. The two yellow tracks show the two ends of the 120R PWM filter resistor. One can see the 1.2 usec time constant and one can see the error voltage on the integrator input. The difference between the two would be the current from the PWM into the integrator. The nonlinearity is caused by a difference of the error pulses when turning the reference on and off, i mean they don't cancel each other.
Second dump shows the same with the OPA140. The error pulses are hardly visible. One could say the OPA140 handles the bandwidth limited PWM pulse correctly. I'd guess without bandwidth limit, there could be nonlinearity again causing "rectification". This time the blue track shows the output of U9.

Regards, Dieter

[Kleinstein]

The extra 120 ohm 10 nF filter looks a bit strange and may effect the linearity. For good linearity the filter should be fully settled for the reference pulse ends. So this may be a little too much filtering, though I like the general idea of some filtering there.

With the 6048 ADC the reference resistor is removed from the circuit and and in the off state there es essentially no DC path at the integrator. So the 2 pulses for turn on / off at the intergrator input behave quite different. There is no compensation between the 2 pulses like it is with many other MS-ADCs that have a constant input impedance at the integrator. The question is if the 1st pulse is not fully settled before the reference turns off and if the pulse changes in area when the input voltage changes. A constant pulse would only add to the offset.
With a BJT based OP-amp some 25 mV at the input is about the amplitude where a long tailed pair input becomes nonlinear and one is leaving the small signal range. A FET based input is often linear over a larger range.

There are quite some interferences visible in the scope traces, also away from the obvious switching times. Is this more an EMI effect from outside/scope, or more a thing comming from the DMM itself ?

[dietert1]

These scope dumps are with input short. The pulse length is 15 usec = 12x time constant, so it settles to 10 ** -5. Then the turn on-delay should be compensated by the turn-off residual charge. Each mod was accompanied by a new linearity sweep (with the scope disconnected!) and the visible effect of the 120R 47nF combination vanished when going to 120R 10nF.
Without the filter, if one applies the full 7 V pulse, the error voltages are much worse.
Yes, the EMI looks a bit disturbing. It was a single shot capture in order to avoid averaging the hum effect on the PWM pulse length. Probably the digital scope with its switched mode power supply needs to move away a little.

Regards, Dieter

Edit: Meanwhile i fixed one of the scope probes and i think that track with more EMI was taken with a "tired" ground lead. Origin of the 40 KHz EMI is the isolating DC-DC converter in the test DAC i am using for the sweeps.

[branadic]

Unfortunately, my 6048 stopped working. I had intermittent resets in the past, which turned out to be a problem of the bridge rectifier, with resoldering the pins helped in first place. This time I will replace the bridge rectifier, (B40C3700/2200), just in case. I don't like the very small rest-ring at the vias, it's a potential source of failure.
Also the flex-connector from integrator board and micro-processor board looks suspicious (small burn marks). Hence why I've ordered a few of those:

https://www.tme.eu/de/details/fsn24a-14/ffc-fpc-bander/te-connectivity/3-1474644-8/?f45b=f45b

and will replace them all, better save than sorry.

-branadic-

[dietert1]

Will you solder the connections? The original connectors are interesting with their copper contacts - at least the one i unsoldered from the amplifier board to prepare the scanner connection. Don't know where low thermal EMF may be important. One problem with the original flat cables is their position in the socket isn't well defined, so one needs to insert them carefully matching the ribbon traces with the contacts in the socket.

I have been looking into replacing the BK7 ADC microcircuit with standard parts and wrote a verilog description of its digital workings with an all synchronous implementation for low jitter. Seems like it fits into a XILINX XC9572XL CPLD. We have old stock of those and it has 5V tolerant IO. Usage of PTerms arrived at 94%. Maximum clock frequency with the 10 nsec part would be 76 MHz.
Unfortunately the BK7 uses several different standards for digital signals. 5V for the interrupt and SPI lines and 12V for the PWM and phase comparator output. The 3.6864 MHz clock input uses L=0.2 H=0.5 V levels - maybe emitter-coupled. Instead of implementing those i might make another Prema 6048-alike first, i mean a 8.5 voltmeter core. One interesting part i found is the 74HC7046 that includes a lock detector.

Regards, Dieter

[branadic]

Will you solder the connections? The original connectors are interesting with their copper contacts - at least the one i unsoldered from the amplifier board to prepare the scanner connection. Don't know where low thermal EMF may be important. One problem with the original flat cables is their position in the socket isn't well defined, so one needs to insert them carefully matching the ribbon traces with the contacts in the socket.

Yes, at least the one between processor and integrator board.
That problem seems to exist only in the black units, the white unit I have on the desk uses connectors with clamping mechanism, so the position is well defined.

-branadic-

[dietert1]

The Prema 6048 is nice to service. If one opens both top and bottom covers almost everything is accessible without unscrewing the boards.

Thinking about the noise record i showed above: I determined 20 second reading noise in 20 V range to be 0.2 uVrms and overall standard deviation to be 0.89 uVrms. From the very start the noise did not look like white noise.
What to expect? The ADC runs with a 3.6864 MHz clock and at the 20 V range limit each rundown is about 3,3 msec of the 10 msec integrator cycle, so it counts roughly 1 200 000 clocks in one second and 24 million clocks in 20 seconds. This makes a digitization step of about 5E-8. How can the reading noise be 1E-8? The instrument firmware supports a digital filter but it wasn't active in my log. Are they cheating?

Regards, Dieter

[MegaVolt]

This makes a digitization step of about 5E-8. How can the reading noise be 1E-8?

Mathematics. If signal samples = 0 0 0 5E-8 0 0 0 -5E-8 then we will get approximately 1E-8 to calculate RMS.

[Kleinstein]

With a sigma delta ADC one is not limited to using only the first / last timing to get the result. One can get a little extra information from other transitions of the comparator.
I can't really follow the calculation of the resolution, but my estimate comes to about the same result: About 70 million clock cycles in 20 seconds. The reference is stron enough for a theoretical 70 V range so a quatization of some 1 µV for 20 seconds and just using the 1st and last comparator time.
The RMS quatization noise is step size divided by root of 12. And with a start and stop part one would still have the root of 6 as a factor and thus some 0.4 µV of quatization noise.

It would be interesting to know how much averaging they use, but it would not need that much to gain another factor of 2 or 3 from a kind of oversampling. This is kind of digital filtering, but on a much shorter time scale, maybe blurring the start and stop of the integration by some 200 ms or so to get 20 comparator readings each and theoretical a factor of about 4 lower quantization noise.

[Rax]

The Prema 6048 is nice to service. If one opens both top and bottom covers almost everything is accessible without unscrewing the boards.
[...]
Regards, Dieter

I agree. One thing to have in mind, though - for anyone becoming overenthusiastic about this - is that the boards are pretty brittle. Typical of boards of that time.
So care needs to be paid not to exfoliate the pads or traces or otherwise damage the boards as one reworks it.

[dietert1]

In a numerical experiment with 500 random numbers of 0 or 1 both average and standard deviation was 0.5. Don't understand how to arrive at sqrt(12). Also there should be more noise from other (analog) sources of noise.

Anyway one could try to check the question experimentally, creating a small modulation of the input voltage synchronous to readout. Lets say one 10 uV different input for every tenth 20 second integration interval. Then logging modulation and measurement results one should see how the readings are averaged, at least after some repetitions of the test.

Regards, Dieter

[Kleinstein]

The  sqrt(12) factor is a classic result: it comes from assuming a variabel true value that leads to quantization errors uniformly distributed between 0 and 1/2 LSB. This may not apply to the test with a fixed zero input if there is little extra noise. Even with this extra factor just the simple use of the first and last comparator time is not enough. So they must use more information to reduce the quantization noise.
Besides averaging over multiple zero crossings another possibilty would be a finer time resolution inside the chip (e.g. using a 2nd interal PLL or multi phase clock) to get a higher resolution to measure the time of zero crosssing.

For testing the ADC function it may be easier to do with a shorter integration, like 1 second. This may other noise sources should get a little less critical and clock steps more visible.
One may want a relatively large step, to actually see the apperture function.

[branadic]

Unfortunately, my 6048 stopped working. I had intermittent resets in the past, which turned out to be a problem of the bridge rectifier, with resoldering the pins helped in first place. This time I will replace the bridge rectifier, (B40C3700/2200), just in case. I don't like the very small rest-ring at the vias, it's a potential source of failure.
Also the flex-connector from integrator board and micro-processor board looks suspicious (small burn marks). Hence why I've ordered a few of those:

https://www.tme.eu/de/details/fsn24a-14/ffc-fpc-bander/te-connectivity/3-1474644-8/?f45b=f45b

and will replace them all, better save than sorry.

Bridge rectifier and flex connector arrived and have been replaced, the black unit is now working again, at least for the moment. I will observe it and once fine I will perform the linearity measurement, that I've planned for quite a while.

-branadic-

[Rax]

Again, not sure this belongs in the "Prema 6048 teardown" thread, but I think this needs to be documented somewhere. Maybe this thread is becoming a compendium on this meter.

I finally got around to replacing the power switch on this 6048. It seems these "COMMODORE 1084s PHILIPS CM8833 Atari SC1435 Monitor PREH ME5A" switches are exact replacements. The only surgical part of the procedure was transplanting the bracket that attaches it to the front panel assembly. It comes with a plastic bracket with correct spacing between the two mounting screws, but too narrow to fit the Prema original screws. So I decided to transplant the original metal bracket.

Other than that - and the rather finicky access (as opposed to the access to the boards, which is excellent as mentioned before) - it's been pretty smooth sailing. My 6048 is again easy to switch on and off (not that it's going to be off for any significant amount of time, but at least I have the choice).

[dietert1]

Meanwhile i made a test setup with a prototype of a Prema BK7 substitute, see schematic. It performs the ADC integrator cycle, but needs more work, for example debouncer for the comparator. The PLL part needs testing, too.

Regards, Dieter

[branadic]

Have you made progress on the software side? I'm asking because that temperature compensation is working and within the specifications on my black unit, but still rather large for my feeling. GPIB access to the temperature sensor data would be a good start.

-branadic-

[dietert1]

Currently i am studying the BK7 substitute. Meanwhile i got the comparator noise sorted out. I needed to review AGnd to get clean switching. The BK7 has two Gnd pins (4 and 14) for a good reason.
Scope dump shows comparator out in yellow and rundown in blue, converting full range input current. Debouncing now works well and there is pretty clean switching with little more than one clock period = 300 nsec uncertainty. After turning off the rundown current source, the integrator error voltage causes an extra pulse of the comparator. It's a TL071..

Regars, Dieter

[Kleinstein]

If the comparator noise is an issue, one may consider the slope amplifier idea found in many ADCs. A similar circuit is also used in precision timing to get low jitter zero crossing signal. The initial gain stage is not only adding gain to get more / faster overdrive at the comparator, but it also is a stage to limit the bandwidth seen by the comparator. The actual BW needed in this case is not that high - it is set by the time from the last reference switching. With normally more than some 5 µs this would mean a suitable BW of some 200-1000 kHz. So no need for a super fast amplifier.  Only a fast comparator looks tempting to get a fast transition, but this also means more bandwidth and thus more noise.

A little more than 300 ns noise from the comparator does not look that good, even with the not so large slope ( ~ 1.4 mA / 0.5 µF = 2.8 mV/µs).

[dietert1]

One clock period is the expected uncertainty when sampling an asynchronous event, with a 3.3 MHz clock that gives 300 nsec. It can't be less. Inside the original meter the circuit will perform at least as well as in the ad-hoc test setup.
Next i have to make the VCO and the PLL loop filter in order to test the circuit at 3.6864 MHz instead of 3.3 MHz. "Learning by doing."

Regards, Dieter

[branadic]

Here is the confirmation of the INL improvement after the OpAmp upgrade with OPA189 on a second unit. Unfortunately, the black unit suffers from larger t.c., still within spec though and slightly higher overall INL.

-branadic-

[dietert1]

Meanwhile i looked at the Prema 5017 schematic that is very interesting. It has the dedicated voltage regulator LM2936 for the HC4046 VCO. It also uses the BK7 microcircuit, but with an additional modulator as a refinement. They call it noise shaping and as far as i understand it is about comparator noise.
I was thinking about another method. There are fast high resolution ADCs like the LTC2386 (18 bit, 10 MHz) that can be used with a FPGA to determine the zero crossing of the integrator run-down by linear regression, hopefully with less noise and sub cycle resolution. Is this a known method?

Regards, Dieter

[Kleinstein]

The use of a fast ADC and linear regression is use by NI instruments as flex ADC. It is described in patent US 6,243,034.
I don't think one would need a super high resolution ADC. Something like 10 or 12 bit may be well good enough, as this would be only for the small range close to zero crossing.

Additional noise shaping (a higher order intergrator / additional low pass filter before the comparator) makes absolute sense. The single chips SD ADC chips are AFAIK all at least 2nd order. So the 1st order SD in the 6048 is more like an oddity.