Prema 6048 teardown

[Mickle T.]

There is no need to parse the 0xCA9E gateway system calls and other LUTs. It is enough to look into the procedures of the parser of the GPIB buffer line and the procedure for communicating with the auxiliary ADC of the temperature sensor through the PIA.

[branadic]

Thanks, but are there any undocumented GPIB commands hidden?

-branadic-

[dietert1]

The undocumented GPIB command will be a Pxx program call with an undocumented number.
I found these: P77, P91, P92, P93, P94 and P97.

The jump table mentioned above by Mickle T has 75 dummy pointers (pointers to RTS instruction = empty subroutine). If necessary one might mod one of those dummy pointers to make an existing subroutine accessible by program number. The Eprom has empty space in case a little wrapper is necessary.

Regards, Dieter

[branadic]

I found these: P77, P91, P92, P93, P94 and P97.

Quickly went through the programs with input shorted, but couldn't observe anything on the display.

-branadic-

[dietert1]

Well, i'm glad if nothing bad happened. Maybe the P9x calls were blocked by the calibration switch.

It's a bit early. I hope i will have a logic analyzer setup for the P6048 after some days. As Mickle T wrote, one should log CPU activity during certain application level events.

Regards, Dieter

[dietert1]

Meanwhile i looked at the relay drivers.
The Prema C32 integrated circuit is a 12 bit shift register with latch and totem-pole output buffers. The P6048 has two of them on the amplifier board and one on the optional scanner. They make a 36 bit shift register that works like SPI. So there are three optocoupler isolated input lines. The CPU starts shifting out 12 bit of MUX control, then 12 bit for U2 and finally 12 bit for U1. Clock period is about 636 usec (!!). The whole transaction takes about 23 msec.

I wired U2 for the logic analyzer and later included the Din of U1 using an analog channel. One can see the 12 bit delay.

I think one can make the scanner using a 4094 shift register. Only the lower 8 of 12 bits are used. Does anybody know how to enable scanner operation? There may be a solder jumper on the CPU board.

Regards, Dieter

[dietert1]

Work in progress..
The LA record shows the temperature ADC readout procedure. The three signals of the temperature ADC are in LA channels 30, 31 and 32. In the zoom the shift clock (pin 7 of 6821, analyzer channel D30) goes high when writing $F3 to $6000. This is the subroutine at $CDE2. If we could give this task to chatgpt...

Regards, Dieter

[branadic]

So you are owner of a Prema 6048, too? Interesting, not sure if I should say "congrats" or "Sincere condolences.".
Have you tested the INL of the 20 V range on your unit already? Maybe we should also test INL in the 2 V range, I guess this is the range with the Prema 6048 showing its strength.

The INL was measured with less than 0.2 ppm in the 2 V range

My unit, that I owned later, was part of the INL test series that Prema performed

Haven't done it myself yet, but maybe worth a try to show the differences between the three units I have, as long as I still have them.

-branadic-

[Kleinstein]

I would not expect the linearity to be much better in the 2 V range. This is still not that bad,as there is at least also no added INL from an extra amplfier stage added as with most other meters.
Knowing about the weak spot around 0 V is already a big plus. Outside that small range the linearity looks quite good.

[Rax]

So you are owner of a Prema 6048, too? Interesting, not sure if I should say "congrats" or "Sincere condolences.".
-branadic-

c'mon, branadic. tell us how you really feel.

[dietert1]

The discussion here convinced me that the Prema 6048 is good - with a minor problem at zero input voltage, but that should be possible to solve. We have a MAX5719 programmable voltage source that can be used with a 100:1 divider to sweep the -100 mV to 100 mV range.

I checked that our meter switches 20 V plus and minus ranges at -41.5 mV (to negative range) and at +41.5 mV (to positive range), like observed on other instruments. After nulling the instrument with 30 mV on its input, the display shows 0 at 30 mV in. Yet range switching happens at the same input voltages - now displayed as -71,5 mV and +11,5 mV.

In the 2 V range the overlap interval is -4.15 mV to +4.15 mV. Near zero one would use the 200 mV range. In this range stability over some hours was observed to be +/- 30 nV. For comparison: A Keithley 3706 with a 3720 muliplexer yielded an average RMS of 15 nV over many channels wired with low thermal shorts. Of course this uses autozero and recalibration by a spare multiplexer channel.

I want to study the mods and tests i proposed above.
Anybody here has that Prema 6048 scanner board? The scanner can be used to implement Autozero and Autocal.

Regards, Dieter

[branadic]

Anybody here has that Prema 6048 scanner board? The scanner can be used to implement Autozero and Autocal.

No, all three units that are currently with me are missing the scanner card.

-branadic-

[dietert1]

Meanwhile i could confirm my recent conclusions from branadics low voltage sweeps. Using a MAX5719 based voltage source with a divider i got exactly the same image. 4 complete sweeps are measured in 20 V range and averaged. We can see the same 9 uV difference at 0 V between + and - range and the same maximum nonlinearity errors of about 15 uV. So we can safely assume that this behaviour is typical for a 6048.

Regards, Dieter

[dietert1]

Here is a similar test of the Prema 6048 2 V range. This time i changed the voltage divider to sweep between -50 and +50 mV and averaged 7 sweeps. A similar analysis separating measurements in + and - range. Range switching occurs at 4 mV when going up and at -4 mV when going down. The difference at 0 V is 2 uV while from the 20 V range result i expected 0.9 uV. This may be thermal EMF of a relay.
The test voltage source with its divider has a specified nonlinearity of 0.16 uV.

Regards, Dieter

[Kleinstein]

I don't think thermal EMF from a relay should make a difference.  The relays for the input before the amplifier would effect the horizontal scale and I very much doubt they would cause an error larger than 1 mV.
The relay K7 for the polarity reversal is doing a reversal in the current flow direction and even if there is thermal EMF at this realy, it would not matter, similar to an effset error of U11.
The points that are more like to make a difference would be leakage currents between the supplies and maybe the different resistor value (5 K vs 50 K) to effect the actual mechanism behind the nonlinearity (e.g. if this is some pulse reaching back to the input amplifier past the filtering from C90).


Another point that can make a difference could be mains hum. Mains hum would modulate the input voltage and this get a mix of voltages more positive and more negative. Added hum would get a bit more nonlinearity from the times when lower in voltage. It would still need quite some hum (2 mV range)  to explain the difference.

The 2 V range may actually have a slight linearity advantage over the 20 V range. The 5 K  resistors R32 would see less self heating than the 50 K resistor R33 for the 20 V range. This would be a small difference in the U³ type contribution to the INL. However this parts seems to be not the main problem due to good quality of these resistors.

[dietert1]

The agreement with branadics data made me wonder whether the nonlinearity might be some problem in the Prema 6048 conversion method. Above i had the trace of the temperature ADC with its 16 bit readout. The main ADC is the same chip, so in order to arrive at high resolution one needs to add lots of conversions.
Maybe there is a rounding problem. With low input voltage their modulation scheme makes the integrator cycle at low frequency. One would expect something like 20 V / 65536 = 3 mV or a fraction of that. If one stays away 40 mV the rounding error might be 3/40*300 uV = 22 uV. Something to check by measurement.

Regards, DIeter

[Kleinstein]

The problem is at the very end of the range, so more like close to the hardware zero. I don't expect rounding problems. It would very strange to have it just at the lower edge of the hardware.

It is more that the PWM ratio may start to reach zero for a few cases with the help of some hum. The ADC uses a quite small (5K) resistor for the reference current. So from the hardware side of the ADC the input voltage could go quite a bit higher than the nominal 2 V or 20 V, more like 7 V or 70 V as theoretical full scale.  The shift from R34,35,36 should be some 117 mV. So this would be only rather short PWM puses to happen and a logical canditate for linearity problem is when the pulses get too short.  I don't know the exact modulation frequency, but it should not be super low.  Asuming some 1 kHz the pwm pulses would be some 1.7 µs for zero input voltage. The clock frequency is also not very high so the 1.7 µs is something like 5-10 clock cycles only.

Normally 1.7 µs should be fast enough for the LT1007 reference driver circuit to settle, so I don't think this should be the problem. The reference off phase is allways long, so no problem there.
Brandic exchanged U11 (the integrator) to a fater OP-amp with essentially no change - so chance are this OP-amp part is also not the problem.
The R29 and C90 RC combination at the integrator input has a time constant in the 6.8 µs range and should thus not be that relevant with the shorter pulses. If at all I would expect an effect with slightly longer pulses / high voltage.

From my ADC build I found the clock generator somewhat prone to interference. Though I don't see a link to short pulses the supply for the PLL part would be a possibly path for strange effects.

[dietert1]

If i do the calculation, i am getting -11,8 mV, not -117 mV.
R35/R36 = 10K/40K = 1/4 Measured: 1,76 V/7,07 V = 0,249
R31/R34=5K/750K=1/150. Checked R34 Label. In-circuit 190 KOhm.
7.07 V / 600 = 11,8 mV

Where is the error?

Regards, Dieter

Edit:
Just measured some timings. At 0 V input the 7.07 V reference pulses to the integrator are mainly 17.635 usec or 15.485 usec at a fixed rate of 10 msec (100 Hz). On average this is about 1/600. CD4046 PLL output is measured as 3.684 MHz. The screen dump includes the histogram. The scope counts how often each pulse length happens. It does not look like a gaussian (noise), but there are two peaks.

[Kleinstein]

The difference in the zero shift come from the range use. It is some -11.8 mV in the 2 V range and -118 mV in the 20 V range.  (the difference 118 and 117 is rounding).

A modulation frequency of only 100 Hz is surprisingly low. I had not expect it to be that low. in this case the OP-amps are likely plenty fast.

The histogram part is interesting.  Chances are the separation in the 2 groups could be due to main hum (50 Hz). There are than 2 cases for the comparator trigger and feedback to happen, both with a 180 deg phase difference for the 50 Hz mains frequency. This could be mains hum from capacitive coupling at the transformer (e.g. between the 2 secondaries for the ADC and input amplifier), as the ADC input relies on the isolation there. So not surprise to find some 50 Hz hum, even of the input of the amplifier has no hum voltage.

A relevant point could be the phase between the 50 Hz signal to the PLL and the PWM signal. With the PWM signal in phase with mains, there could be a point that coupling from the PWM / reference swiching towards the PLL could cause problems, like some FM modulation and this way an INL error.

[Andreas]

Hmm,

I am asking myself.
What about the measurement value (noise) distribution when approaching 0V at the input.
Does it stay gaussian or does it get unsymmetrically due to clipping at zero?

With best regards

Andreas

[dietert1]

Meanwhile i noticed that the two pulse length peaks at 0 V input vanished and became one with gaussian character when i nulled the instrument. The polarity relay clicked and the scope started counting at 16.5 usec (in the middle). Nulling the instrument again, it returned to the double peaking.
The same happened when i watched the histogram while sweeping the input voltage. The minimum pulse length observed before the instruments switches the polarity relay was 10 or 11 usec. In this moment i am not shure in which position of the polarity relay the double peaking happens.
As the ADC cycles the integrator at 100 Hz and in each cycle the maximum count is 65535 (16 bit), the maximum total in 1 second is 6 553 500 counts. This would be the full 70.7 V range in the so-called 20 V range. With the measured PLL clock frequency of 3 684 000 Hz the actual range limit of the 20 V range is at 39,7 V. At 20 V input voltage the duty cycle of the reference current is about 50 %.

Regards, Dieter

Edit:
Meanwhile the scope shows a trace of measured pulse times. While the negative range looks clean, for the positive range there seems to be 50 Hz hum. Both records are with DVM inputs shorted.

Edit 2:
At 20 V input the current from the front end is 20 V / 50 KOhm =0.4 mA. The DAC generates 7 V / 5 KOhm = 1.4 mA pulses. If you do the calc, duty cycle of the DAC will be only 30 %.

[Kleinstein]

Seeing the split histogram only with 1 polarity setting could be an artifact from hum coupled in via the scope ground. The polatiy realy changes how the grounds are related and this is expected to change the amount of hum.

The splitting to the hum is still rather small and this should not cause clipping. There is still quite some headroom (e.g. some 10 mV in the 2 V range) before this happens. The splitting due to the hum in only in the 1-1.5 mV range. In addition is looks like much of the hum seen is due to the scope and likely not present in normal measurements.

The 2 groups would be equally frequent and alternating between them. With intgration of full PLCs there should be always the same groups involved and thus normally no extra noise.

The noise may actually change with the input signal, as the reference path is only connected when actually needed. This may lead to more noise when measuring a significant voltage. Still this wold not be with a few 100 mV, more like a thing going half the range and than it is tricky to separat it from reference noise.

[dietert1]

I thought a bit before connecting the scope. The Prema 6048 front end has two isolated parts, the amplifier and the ADC. The amplifier output connects to the ADC input via the polarity relay, without any other external connection. Hum may come into play via the common mains transformer. Scope Gnd is connected to the Gnd of the ADC as i was looking at the reference source. Don't see how the scope introduces hum, as its Gnd is the only external connection of the DVM frontend.
Anyway, i will connect another DVM to the ADC input in order to check whether the low voltage nonlinearity stems from the ADC.

Having a closer look at the HC4046 VCO in the ADC, i found a design problem. They made the VCO range adjustable instead of the offset frequency. This means the VCO range is huge (maybe +/- 25 Hz) in comparison to what is needed (maybe +/- 2 Hz) causing unnecessary phase noise. And the VCO can get its own 5V voltage regulator. I found a LM2950-5.0.

Regards, Dieter

[Kleinstein]

For the hum part in normal use the amplifier ground part including the input terminals acts a bit bit shielding around the ADC part. With external hum much parts are floating and could move in parallel. With the ADC part grounded via the scope hum that couples to the amplifier part can now act on the ADC input, at least for 1 polarity.

Because of the relatively low modulation frequency of only 100 Hz the phase noise is not as critical as with other MS ADC with with fast modulation (e.g. HP34401 and 3458 use some 330 kHz). Some of the 100 Hz synchronous hum causing the frequency modulation may however effect the linearity. This would howver not be much for the near zero range, but worse the larger the voltage. This may be the reason for not using a classical LC based VCO, as this could react to an 50 Hz magnetic field or mechanical hum.
I am not sure if setting a higher low frequency limit for the VCO in the 4046 would help very much. There are intrinsic limits to the accuracy of the low power relaxation type VCO.
Changing the resistor also changes the PLL loop gain. So changing to a smaller R55 and larger R56 could change quite a bit.

Having the logic part of the ADC chip and the VCO on the same supply without much filtering could indeed be an issue. A separate regualtor or better filtering of the VCO supply could be a possible point to try. The 4046 VCO has quite some sensitivty to the supply.

[dietert1]

No sorry, the HC4046 VCO gain and offset confusion they made actually caused variable VCO gain - bad for control loop stability. I am correcting that mistake.
In my current setup the VCO base frequency adjustment has 3.19K. The other resistor that determines VCO range is 100 KOhm (R1 in HC4046 datasheet). So the VCO range is much smaller than before. The control loop remained stable but can be improved. For example the integrator U6 needs a diode to avoid integrating to the negative side, where the VCO limits. Frequency noise as measured by the scope reduced by 3.5.

Regards, Dieter

Edit:
Just found a little trap while nulling the instrument. When you press the null button, you can hear the polarity relay without any delay. Seems they assume you already had the inpot short for some time and there is a valid null measurement for the current polarity. So they switch the relay to acquire the null reading of the other polarity. With long integration times, if you insert the short and press the null button you may get "Error 4" if the last valid reading is outside limits, like open inputs.