I have finally hooked up the NVM to start measuring some external voltages, and I can tell that it will be a challenge to maintain the performance of the internal short. The change in offset between shorting the inputs internally and externally is not much. With the modulator frequency at 1800 Hz and the ADC switches at 200 Hz, I saw 37 nV and 45 nV respectively for internal vs. external. There are Pomona low thermal EMF binding posts on the front panel, and I was using a piece of unfluxed solder wick as the short. However, to get decent readings, those binding posts need to be covered from drafts. The susceptibility to mains-frequency noise is much greater, unsurprisingly, though the situation with a short is not too dire when everything is closed up. I found that the powerline noise would just alias back to lower and lower frequencies when averaging blocks of samples if I used frequencies that were not a multiple of 60 Hz. I tried 315 and 1770 Hz, and they were a mess. With 1770 Hz, there was a peak at around 350 mHz.
Using a 49k95/50R divider, I measured some voltages from my power supply, and the issue was much worse. For some reason I cannot explain, the gain on both channels is 25% lower than what it should be from the schematic (I am using values of 2002 and 202 for the high and low gain settings). The issue does not seem to be with the chopper stage - on the high gain setting (1001x), I measured a gain of 1009 for the front end and 2020 at the ADC inputs. From the limited work I have done to diagnose the issue, I know it is unrelated to the sample rate of the ADC, as I get the same numbers with 500 kSPS and 2MSPS.
The additional inductance from putting a short at the front panel definitely causes some gain peaking for both settings. I think it would probably be best to slow them both down a bit by increasing the integrator capacitance from 47 to 68 pF and same with the feedback capacitance. As I was investigating this and running some simulations, I think I had conflated SPICE not converging with instability on the 101x gain setting. The pole-zero network in the feedback for that doesn't seem to be crucial (I took it out on the board too). The point where open loop goes >0 dB with positive feedback is at >100 MHz, and this does not seem like a real issue with the parts I am using because the diff amp and the ADA4625-1 just don't have that kind of bandwidth. The phase margin at 40 dB closed loop gain does leave a bit to be desired, but increasing the value of the caps as above should work. I think this is important because the increased noise from the low gain setting relative to the analog out is almost certainly related to aliasing, and having the gain go to 60 dB at higher frequencies was probably not helping. My general sense is that you need to take antialiasing very seriously with oversampled SAR ADCs at this kind of resolution. Clearly, it is not just the SAR ADC though, which is apparent from the low frequency spectrum with a 315 Hz modulator clock.
Speaking of aliasing, I looked at the noise from the PSU, and it is definitely a target for improvement. I think the +8V5 rail noise is making it to the analog outputs, but this is still at the level of a strong suspicion, and I haven't powered all the rails with linear supplies to confirm this. The noise spectrum of the +8V5 rail has a lot of lower frequency stuff (~10 kHz and harmonics, switching at 2 MHz). I took a spectrum of all the rails (attached) using a test board with some resistive loads. I know from some previous experiments that the noise spectrum of the +8V5 rail gets better with heavier loads, so I think that it is a combination of the controller going into burst mode and ring-off when the switch goes high impedance. I have made changes to the schematics for the next revision and have added another Cuk (not inverting) to power the ADR1399 heater based on Andreas's notes. It may be better to actually use the same topology for the +8V5 rail, as I was able to get very good efficiency in simulations while staying in CCM at light loads (of course, this requires very large inductors). I think that staying in CCM is crucial for this application because of the noise sensitivity, and the radiated emissions from ring off could easily alias into the pass band. I don't see a lot of high frequency content in the spectra for the primary rails supplied by the SMPS board, but I haven't checked around with an E field probe to see if there are radiated emissions coming from high dv/dt transients.
Ultimately, I don't know that it will be optional to synchronize the modulator clocks with the mains to get good performance here. I have an isolated input I can use for such a clocking signal, and I have designed a board to drive it. I am still learning about DSP, but from what I can gather, FIR filters, like a block averaging filter, will generally be susceptible to aliasing unless the spurious signal lands in a null. I feel like it would be helpful to use an IIR filter for the offsets to mimic what I did with the proof of concept version with Rs and Cs to reduce the susceptibility to noise, but I will have to test this. I have attached some spectra I took of the analog out and power supply. The modulator clock was 1800 Hz unless otherwise specified.