Thanks, I need to ponder this a bit.
Further, the 160ps pk-pk variation in the width of the pulse need to be taken with a grain of salt, as the Wave Ace 2032 specifices:
Trigger and Interpolator Jitter: 0.4ns pk-pk
Be careful with equivalent-time sampling, as each period has a different jitter and it'll be combining them all together. That's fine for looking at histograms, but not for interpolating periods from the acquired data. I've been disabling ET sampling. In single-shot mode, I've been interpolating between acquired point in order to determine the timing of the rise, to a resolution better than the sample rate, though this relies on a fast rise time of the input signal (since the oscilloscope's amplitude usually has significant noise). I use a P6243 1 GHz active FET probe for this.
In your case, a period of 166ps, and I think that you were looking at the single-period jitter? You have enough memory to acquire an entire period of the clock, so can sample at 2 GSa/s (500ps resolution). If you calculate the period based on the rise-to-rise of what's on the screen, the trigger jitter won't matter. On the other hand, it will matter if you enable ET sampling since it'll mess up the interpolation.
How the manufacturer likely measures trigger jitter is by acquiring a very fast edge, and comparing the t=0 mark on the screen with where the interpolated acquired data actually passes the trigger voltage. Do this enough times and you'll find the pk-pk and the RMS jitter.
In my measurement, I often was looking at signals with periods of about 1 ms. I used a delayed trigger mode (setting the delay to the signal period), and plotted a histogram of the acquired data around the trigger voltage on the screen. This measurement is very much influenced by the trigger jitter. If I knew the trigger jitter, I could have subtracted it out, but didn't. The Tek TDS784D has a datasheet specified jitter of 7ps (unsure of if it is RMS or pk-pk). Its max sampling rate is 4 GSa/s.
I've been distracted by work recently, but also looking into building something like the TAPR TICC in order to better characterize the jitter. I breadboarded a TDC7200, but was getting about 80 ps RMS jitter (twice the datasheet value of about 45ps RMS). I then got sidetracked by looking at FPGA-based TDC which made me run into some bugs in the Lattice MachXO2 compiler... The MachXO2 should be able to be at least as accurate as the TDC7200, probably much better, with the use of an external PLL.