JFET input stage low noise amplifier

[MK]

Yes, I'll do when the semi-soldered version works.
There are too many versions otherwise I have to keep track of.
I don't want to usurp this thread.

One more thing with the IF3602:
Does anybody know how this plateau in the noise happens?
X-axis is in KHz.

I think humps are G/R noise, the hump depends upon temperature and the recombination time for the impurity that is present.
I believe that if you cooled or heated the hump would move frequency or even disappear.
Some people have seen humps appear when they have cooled a device to improve its noise!

MK

[CurtisSeizert]

I have spent far too much money on IF3602, at €80+ a pop.
They are all individuals.
The new data sheet is closer to reality, but with these data it is
no longer interesting.
Yes, they offer a selection service. I guess, what we get at Mouser
is what is left over. :-(
The data sheet guarantees next to nothing. And this capacitance!
You are better served with On Semi 3910, 4 pcs. in par.

Looking at that makes me wonder about paralleling a bunch of JFE2140s as another possible alternative.  Much better matching, 20x cheaper, etc. To me, these new JFEx140 parts hold more appeal than the LSK389/LSK170 because the noise performance is similar, gate capacitance is lower, and the matching is much better.

Have you noticed spread on the 1/f corner frequencies for these IF3602s?

Do the signal relays and analog muxes have better bandwidth properties at 100kHz than using dpdt toggle switches directly? Or perhaps the design was influenced for possible future digital/mcu control?

One of the relays is momentary.  It shorts the resistor at the input HP filter and forces the current to go through a 2k2 resistor when changing sources (between the calibration jumper header and the SMA input).  It is controlled by a 555 timer to activate the relay for 5s whenever the source toggle switch is flipped.  The settling time of the first version was a major irritation (usually took overnight, sometimes required flipping the power switch), but this one always settles within about 30 min.  The benefit to the other relay (K1) is that it doesn't get in the way of your thumb (as much) when you're unscrewing the SMA connector.  I had originally put relays where the muxes are when I was doing layout, but the muxes are smaller, and the relays were a little more awkward to fit in with the shield, which is there to restrict air movement around the sensitive nodes.

The nice thing about having a JFET op amp is the low current noise going through R19, and there is minimal cost difference between the 4625-1 and 4625-2.

Note that R19 is paralled with C16-R17, but that's not a lot of consolation - that branch also has 1MΩ impedance at the corner frequency, and low frequency is exactly where noise is worst.

The corner frequency is below the range I was looking to measure for this reason - the impedance of C16 at 0.1 Hz is 234k, so current noise from the noninverting terminal at that frequency mostly does not get transformed to voltage noise by R19.  Also, the signal is 200x larger at that point, so the effect would have to be very significant to have an impact.  I did take the output signal of the first gain stage (between TP1 and TP2) run it through a G=50 inverting amplifier, and there was no effect on the voltage noise spectrum.

If anyone is curious, here is the noise voltage spectrum for LF noise of the +7V5 rail (generated with an LT3042 with the set resistor bypassed by a 22 uF Ta cap).  I measured noise up to 25 kHz on the positive rail, and it is actually quite good above 10 Hz, but I cannot find that trace at the moment.  The positive supply rejection should be about the same as the CMRR of the op amp, which is >100 dB, but I wonder if in practice capacitive coupling might cause some of this to appear at the input. The 7V5 rail is actually the first inner copper layer (should have been ground, and was ground on the previous version). Perhaps I can bodge in some ridiculously large cap to bypass that set resistor and see if that has an effect also.  The -7V5 rail is the same story in noise, but it's shielded from the input signal better (by the +7V5 rail) and supply rejection is improved by the current sink, so I believe if one of the rails is the culprit, it's probably the positive one.  I may try a LT6655-5V driving the set pin of an LT3040 for future designs.

Curtis

Curtis

[Gerhard_dk4xp]

Have you noticed spread on the 1/f corner frequencies for these IF3602s?

No, that was quite consistent with my 15 or 16 samples and like typical in the data sheet.
I did not test all of them.

Note that the 1/f corner is somewhat unfair. Much noise in the flat part of the spectrum
tends to improve the 1/f corner.

Rubiola does not like it. He has a different set of coefficients.
<    http://rubiola.org/pdf-articles/journal/2004rsi(rubiola)low-flicker-dc-amplifier.pdf      >
That's a most interesting web site.

[CurtisSeizert]

Have you noticed spread on the 1/f corner frequencies for these IF3602s?

No, that was quite consistent with my 15 or 16 samples and like typical in the data sheet.
I did not test all of them.

Note that the 1/f corner is somewhat unfair. Much noise in the flat part of the spectrum
tends to improve the 1/f corner.

Rubiola does not like it. He has a different set of coefficients.
<    http://rubiola.org/pdf-articles/journal/2004rsi(rubiola)low-flicker-dc-amplifier.pdf      >
That's a most interesting web site.

The reason I asked is because that was the major difference between the two IF3602 amps I built - the first had a 1/f corner around 1-2 Hz, the second was 10-20 Hz.

In the end, this amp was meant to measure power supplies and voltage references, and the noise floor is adequately low to characterize the 1/f noise of those pretty well.  Actually, the wideband noise density of 1 nV/rtHz is more of a limitation because it will add significant error to measuring the noise of, for example, the 7V5 rail of this amplifier, which is around 2 nV/rtHz using an LT3042.  From using this a bit recently, the key advantages are the bandwidth and the settling time.  The settling time is only about 2 minutes for most things, but it helps to wait up to 15 min for the quietest DUTs. The physical act of changing sources and putting everything back in the cookie tin takes about as long as settling. 

I did some captures on my scope to get measurements out past the Nyquist limit imposed by my 34465A, and I noticed a 27 kHz oscillation on an ADR1000 board I made that (I think) was actually appearing as popcorn noise when I measured the reference directly because of aliasing.  I'll put a couple of the spectra below.  I had a bunch saved up, but I need to reprocess the captures because I lost the plots when my computer crashed.

[Gerhard_dk4xp]

10-20 Hz 1/f corner sounds quite OK for a FET to me.

Is the noise in the flat region comparable between the two amplifiers?

Are the gate resistor and the input coupling capacitor the same?

Having too small a coupling capacitor can result in a lower -3 dB frequency
that is still completely OK, but the noise behavior will be very different.
Sub-1nV/rtHz amplifiers need the noise of their bias network shorted
through the low impedance DUT. The DUT MUST be low impedance
or it would generate too much thermal noise alone from this  and would
not be worth the amplifier.

That noise rises faster than 1/f, more like 1/f**3 IIRC.
I had that effect in my 10*2*ADA-4898 op amp amplifier with 10K bias-R
and 100 uF foil coupling cap. You see the effect in most of my early plots.
Changing that to 4700uF wet slug tantalum removed the noise rise for good,
but had other drawbacks.

When your analyzer is 2 channels and can do cross correlation, you may not
need to drive amplifier noise very far. XC can bring you another 20+ dB.
I tried it with my 89441A and it was spectacular. So good that I assumed
operator error. I will retry that.

Gerhard

[Gerhard_dk4xp]

I have continued work on the 16 x 3910 this weekend.
The horizontal part of the purple trace should be at -180 dBV, gain is not yet calibrated.
All that counts is the difference between the two traces. 10 dB difference would say
that the amplifier's own voltage noise is 10 dB below the noise of a 60R resistor.
10 dB below 1nV/rtHz is 316 pV/rt Hz.
That*s in the range that could be expected, but the 1/f**3 part still starts somewhat early.

NSVJ3910 and CPH3910 have identical data sheets and the same marks on the chip.
Once taken from the tape it's impossible to tell them apart.

The 0-TC point of the 2sk2394 is near Idss. That is too much current with 16 pcs. in parallel.
Since I have no feedback around the FET, the 3910 seems better for my amplifier even if
the 2SK2394 should feature slightly less noise.


Gerhard

[Gerhard_dk4xp]

I could tame the steep noise rise below 50 Hz a little bit.
My Agilent 89441A has less 1/f on the more sensitive ranges, i.e. full scale = -30 dBm.
The preamp gain can then be reduced.

The major change was at the LT3042 that feeds the input cascode. The 3042
features 2nV/rtHz at 10 KHz, but below 20 Hz it quickly gets worse. I increased Cref
from 4.7 to 47uF tantalum. Now it takes two minutes until Vcc is stable, but
probably one can play with the PowerGood divider to speed it up somewhat.

Then there is a now a 1000u oscon on the 13V5 line. It seems to help somewhat,
but I'm not yet sure how much. There is no space to insert something really big.

Gerhard

[CurtisSeizert]

I could tame the steep noise rise below 50 Hz a little bit.
My Agilent 89441A has less 1/f on the more sensitive ranges, i.e. full scale = -30 dBm.
The preamp gain can then be reduced.

The major change was at the LT3042 that feeds the input cascode. The 3042
features 2nV/rtHz at 10 KHz, but below 20 Hz it quickly gets worse. I increased Cref
from 4.7 to 47uF tantalum. Now it takes two minutes until Vcc is stable, but
probably one can play with the PowerGood divider to speed it up somewhat.

Then there is a now a 1000u oscon on the 13V5 line. It seems to help somewhat,
but I'm not yet sure how much. There is no space to insert something really big.

Gerhard

Is that change in LF noise performance just from the increased bypass capacitance on the LT3042 Rset? Is your amplifier a diff pair-op amp input stage? If so, I would have expected more attenuation of Vcc noise.  In any event, I would not consider 2 minutes of warm up time to be that big of a problem, so that is a nice improvement!

Given the issues with designing around the IF3602, I am working on a major revision to the amplifier I am working on that uses 8 paralleled JFE2140s with independent current sinks on the tails for each in two paralleled gain stages (for 16 total JFET pairs). The matching between parts on these is at least as good as the matching between the two individual JFETs in the IF3602 - in a quick sample of five parts I got a spread from 798 mV to 810 mV VGS at 500 uA. The differential between VGS for all these was <1 mV, and 4/5 were <500 uV. In simulations, the noise reductions when increasing the tail current beyond 1 mA for each JFET pair seemed to be tempered by the need to lower the impedance of the current mirror load by decreasing the emitter degeneration resistor values if the supply voltage was to remain the same. What Is are you running the CHP3910s at?

Curtis

Curtis

[Gerhard_dk4xp]

Yes, the only important change is the increase of the capacitor across Rset from 4u7
to 4u7 + 47u.  LT wrote "up to 22u" somewhere in the data sheet text. I'm not sure
if this is a real limit or only a level of despair.
FET current is abt. 45 mA.
The picture is quite close to the actual circuit. There is a thermal noise generator on Vcc.
The 2 nV/rt Hz are acceptable, but 20 nV/rtHz would be a desaster. A LM317 would deliver
much more, everywhere.

Note that the LT3042 noise does not behave like 1/f. It rises much faster. When the cap
across Rset is ineffective, you get the full broadside of 135K voltage noise (in my case with 13V5)

Below 10 Hz, the noise of the 10Meg gate resistor also starts to play a role. (red trace)
It is shorted by the 10u input C through the DUT. INCREASING the Resistor makes the
noise contribution smaller since the shorting is more effective. Same for a bigger coupling C.

A differential setup would require 4 times the number of transistors for the same performance.
Somewhere is a limit, although H&H have a differential amplifier with 64 BJTs in their
book "Art Of Electronics", ed. 3.

I have built an asymmetric quarter of it; it delivers the promised 70 pV/rtHz. I accepted the
ugly Cin since most interesting DUTs have DC offset anyway.

The bottom right IF3602 pair in reply #11 has quite a lot of offset.

[Kleinstein]

When using a differential pair, there is much less effect of the supply noise.
The 1 FET  amplifier has noise from the FET and noise from the supply / current source (LT3042 + resistor)
The differential pair has the noise from 2 FETs and very little noise from the supply.

So the 2 nd FET kind of competes with the LT3042 based current source and it is not clear which way is lower noise.
For the higher frequency range the LT3042 can use filtering, but this does no longer work at the low frequency end.

[Gerhard_dk4xp]

The differential solution takes 4 times the number of low noise transistors
from the start, with a corresponding increase in input capacitance.
With the IF3602, that approaches a nF in just one.

OTOH, having a clean VCC is easy. The LT3042 with a "large" cap == 47u
does it for the 300 pV level. If that should not be enough, I could return
to the capacitance multiplier with a Zetex 851 / 951, or the smaller SOT-23
relatives. I just wanted fixed voltages for my operating point window comparator,
which is kind of a luxury problem, just reducing waiting times.

Full Lithium ion cells deliver 4.2 Volts and can be discharged down to < 3.5 V.
That is quite a moving target.

With a higher Vcc one could use a larger load resistor, both providing more
gain before the noise injection point and better isolation of Vcc from the signal flow.

Cheers, Gerhard

[MK]

Hi Gerhard,

I noticed your comments about the noise figure being optimistic for the 3910's. I noticed the same thing with the BF862's, so I had a tweaked model where I adjusted the noise figures to better match the reported numbers, a computer crash lost the model, but you could tweak the parameters to match the numbers you see.

[Gerhard_dk4xp]

I've tried to massage the 2SD2704 in reply #10.

Looking at my library I found that I have no models of
interesting low noise / high gain transistors that include 1/f data.

Does anybody else? Or has anybody measured that himself?

The interesting parameters are  AF and KF in the spice model.

[MK]

I've tried to massage the 2SD2704 in reply #10.

Looking at my library I found that I have no models of
interesting low noise / high gain transistors that include 1/f data.

Does anybody else? Or has anybody measured that himself?

The interesting parameters are  AF and KF in the spice model.

This page seems to help:
https://www.youspice.com/spice-modeling-of-a-jfet-from-datasheet/5/

[3roomlab]

I've tried to massage the 2SD2704 in reply #10.

Looking at my library I found that I have no models of
interesting low noise / high gain transistors that include 1/f data.

Does anybody else? Or has anybody measured that himself?

The interesting parameters are  AF and KF in the spice model.

This page seems to help:
https://www.youspice.com/spice-modeling-of-a-jfet-from-datasheet/5/

yea the KF and AF
I have tried to DIY the values before quite sometime ago by randomly trying values
** edit : I think I maybe getting a hang of it.

[MK]

From memory the exponent value gives the steepness at low F, but they do interact, it would be helpful to have that pspice curve fitting program available to use! I never did get the corner frequency correct either., but could get it to give numbers that corresponded to the consensus values of noise found by several contributors.

[3roomlab]

I've tried to massage the 2SD2704 in reply #10.

Looking at my library I found that I have no models of
interesting low noise / high gain transistors that include 1/f data.

Does anybody else? Or has anybody measured that himself?

The interesting parameters are  AF and KF in the spice model.

i found some infineon models with AF / KF (2016 library)
BFP183 BFP196 BFP193 etc 30++ models
I did not browse the latest file at the website, there probably are others.

[CurtisSeizert]

The differential solution takes 4 times the number of low noise transistors
from the start, with a corresponding increase in input capacitance.
With the IF3602, that approaches a nF in just one.

I ended up doing a revision and replacing the IF3602 with 16x JFE2140, but I kept the differential amplifier input stage (with some modifications) so that measurements would be easier with my setup. The process control on the TI JFETs is much better. I measured 42 samples taken from three orders, and the highest and lowest VGS at 500 uA were 55 mA apart. The maximum VGS offset I found was 1.13 mV.

The total tail current is rather large at 22 mA, but the noise and bandwidth performance are reasonably good. LF noise (0.1-10 Hz) was consistently between 3.0 and 3.1 nVRMS, and the wideband noise is a bit below 600 pVRMS. My single cookie tin is not fully shielding from 60 Hz pickup and odd harmonics in the 10Hz-10kHz spectrum.

Total gate leakage current is comfortably below that of a single IF3602, so the amplifier settles faster after opening the switch that shorts in the input HP filter resistor. From the specs, the total gate capacitance should also be lower, but I have not measured this. The -3 dB point is about 2.5 MHz with OPA1655 gain stages. There is some peaking before gain rolls off, so I will likely reduce the bandwidth to flatten the response. I have not investigated which stage is responsible for this behavior yet. It may be possible from simulations to increase the bandwidth further, but I think this is good enough for me.

Curtis

[1audio]

Do you have a sense of the input C and input bias current with 16 JFETS? The original article is no longer at that link. Can you post your circuit?

[CurtisSeizert]

The total gate leakage current is in the neighborhood of 9 pA (92 uV across a 10M resistor), or about 500 fA per JFET, but that assumes no leakage to ground other than through that resistor. I haven't measured the total gate capacitance, but it should be 240 pF based on 16 JFETs at 15 pF apiece (datasheet values). I think that applications that required lower gate capacitance would work better with fewer paralleled FET pairs perhaps running at a higher tail current. The 10 Hz 4th order LP filter does not work as drawn, so I will likely change it to a higher frequency or delete it altogether.

I simplified the schematic a bit and deleted the parts that I did not populate. I have been busy with other things, so I have not dealt with the gain peaking issue. My guess is that it is from the first stage because I kind of titrated the feedback capacitance up on that stage until it stopped oscillating (it took 45 pF).

Curtis

[1audio]

Impressive work.
Looking at it I think the cascode could reduce the input capacitance significantly. Might be worth measuring. In any case 240 pF should not be an issue in most applications of something like this, nor the input leakage, however it will change a lot as the Jfets heat up.

It looks like a natural for ferrite beads on the gates of all those FET's. I have had to deal with internal oscillations there a lot.

In a similar application I used depletion mode mosfets for the cascode. They work really well and eliminate the bias stuff for the cascode.

[Kleinstein]

For the input capacitance the full data sheet value does not apply for the visible input capacitance. The value in the DS is usually for a common source circuit. With the differential amplifier the source moves essentially like the input and the capacitance is thus not effective.
The gate capacitance can however still be effective in the very high frequency limit. The transition can be a reason for the sometimes observes negative input impedance, that can lead to osciallation.

The choice of the OPs in the current sources is a bit odd: the OPA2191 has quite a bit of low frequency noise. My choice here would be more an OPA2202.
There is no absolute need to fully separate current sources. A single current source and than resistors for current sharing between pairs should be good enough.

[Gerhard_dk4xp]

Since the bias current seems to be important here:

This is an heroic effort of someone at ETH Zürich in Switzerland:

<   https://arxiv.org/pdf/1708.06311.pdf    >

My own amplifier does not make big progress, I must first create
a 100 MHz clock oscillator with extra low phase noise for a
15GHz synthesizer.

But 100u tantalum seems to work nicely to push down the noise corner
of a LT3042.

That noise peak  might be that stability problem that haunts me
so long already. Try a much faster Op Amp  or simulate the
real part of Zin. =  re( Volt_input_signal/ current_input_signal).
It could be negative at some frequencies.


regards, Gerhard

[CurtisSeizert]

I have not had much time to do a lot of in circuit testing outside of verifying gain and noise performance, so I can look into these things, but it may be a few days. From simulating the circuit with various op amps on the input stage, I suspect the gain peak is related to that. I attempted to make a DC-coupled version using an AZ stabilization scheme similar to the one in Linear AN-61 (using an LTC2058 and larger Cf on the bias control circuit), but I found the noise performance at <1 Hz to be far inferior. In that version I used LTC6240s as the op amps in the input stage, and those required larger feedback capacitance to ensure stability (I believe 100 pF was the minimum). Importantly, in both cases, the results were consistent with simulation. With more V+ headroom, there would be a larger choice of op amps that could be used, and some of these could allow operation at higher frequencies.

That said, I wanted to be able to operate with most of the charge on 4 series Li batteries, and to me that was more important than pushing the limits on bandwidth, as the amplifier already covers 7 decades. Keeping the supply voltages down was another way to minimize power dissipation that might cause thermal gradients that could spoil the LF noise performance. Finding an op amp for the gain stage that has low Ib, reasonably low Is, and can operate with 2-2.5 V headroom on V+ took a lot of data sheet reading. I was a bit nervous that the poor LF noise performance of the OPA1655 would show through, but the gain of the input diff pair seems to have been large enough to avoid that issue.

An observation I made that may be more informative to people who are more experienced in the art than I am (which I assume is probably everyone who responded to this post): Good LF performance (<1 Hz) is only accessible with magnetic shielding. Thermal shielding does not really improve things from having the board just sitting out. Outside of 60 Hz pickup (and harmonics), the HF noise is relatively unaffected by shielding. The board is a 4-layer with V- and most signals on the top, solid ground planes on both inner layers, and V+ (with some signal) on the bottom. I can post gerbers and project files when I've got some more time if anyone is curious about the layout. The input stage is about as tight as it can possibly be.

For Ib and thermal performance, the overall current draw is 47 mA on both rails, and no parts get noticeably warm at the maximum battery voltage (8.4 V for both). Once I have drilled the necessary holes in the enclosure I plan to use, I'll get a thermocouple in there to see if that changes anything and provide more quantitative results. I had expected the thermal performance to be worse than it has been, so thankfully I will not have to machine any copper parts and add peltier cooling to keep things in check. That would probably be too much work anyways.

Regarding the choice of the op amps for the current sources and the overall configuration thereof, I am satisfied but perhaps not pleased with that part of the design. I am relatively certain the op amps do not have a significant impact on the overall noise performance there as most of the noise comes from the voltage reference. I did simulations with variously mismatched JFE2140s to get an idea for attenuation of the noise of the current source. I cannot remember the exact numbers, but I do remember it was enough to prioritize supply current, package size, and worrying about other parts of the design more. Perhaps the OPA2202 would have been a better choice, but it would probably work well either way. Given the apparent level of process control on the JFE2140s, this may be overkill, but when one of the pairs was acting like a short I was very happy that I only had to pull off 2 JFET pairs instead of 8.

Anyways, given that the performance of this design is already far beyond what I need, I am not sure how many iterations I will do. @1audio if you are interested in taking the design further, I am happy to share the kicad project files. The layout was quite time consuming.

Curtis

[CurtisSeizert]

It looks like a natural for ferrite beads on the gates of all those FET's. I have had to deal with internal oscillations there a lot.

I was doing some more testing and found that the circuit becomes susceptible to oscillation with increasing source impedance. This begins to show on the 60R calibration resistor and gets quite bad with the 1.5k resistor. The peak was originally at 1.78 MHz. Reducing the amplifier bandwidth by increasing feedback capacitance to 150 pF helped reduce the amplitude of the oscillation somewhat and the frequency of the main peaks is now 1.09 and 1.55 MHz. The -3 dB point is about 500 kHz for the first stage now. The behavior is the same when connecting sources with any significant length of coax (more than about 20 cm). A 50 ohm terminated length of coax is similar to the 60R calibration resistor. If I replace the termination with a short, the oscillation is still present, but some of the harmonics become larger in amplitude than the fundamental. For 1 m (with Cf=45 pF, with a fundamental of 1.78 MHz), a much larger oscillation occurs at 10.7 MHz. In this case the frequency of the oscillation depends upon the length of the cable used. The 10.7 MHz oscillation was about the same amplitude after the first stage (Av=201) as it was after the third stage (Av ~ 10k total).

I took a couple screen captures from the scope with its integrated FFT function to show what this looks like in the frequency domain and processed a longer raw capture because this scope for some reason has no way of doing a log scale x-axis with FFTs. I made a Bode plot for the output of the 100 kHz LP filter also, which I will include for posterity, though it isn't really relevant to the oscillation issue.

Is there a general solution to this type of problem that is more elegant than reducing the bandwidth of the first stage further? My sense is that these oscillations are at too low a frequency for ferrite beads to be effective, but my experience is limited on this. I have also seen lead networks between the legs of the differential pair that I assumed were put in place to ensure stability. Are there general approaches to troubleshooting this problem or good resources to check out?

Curtis