Is the quest of replicating a Datron 470x calibrator totally foolish or crazy ?

[DC1MC]

Sent you a PM.

 Me as well

 Cheers,
 DC1MC

[branadic]

Any progress on this topic?

-branadic-

[DC1MC]

Yes, I've got the capacitors and poor-man OP, collected the precision resistors, some P and N JFETs, and now I want to place a big order on Arrow to assemble a collection of OP suitable for testing (Kindly please contribute to my fresh topic in this forum regarding the OP), also Kelvin cables for my little multimeters and I want to come with a schematic this month after some experiments.

Also looking for one of these small CPLD/FPGA boards to implement the PWM generator, I've looked at your experiments with ATtiny and friends, this stuff really has jitter and bundle of other problems, I'll take my chances first with the original Datron schematic with JFET switches, with a bit of improvements from Kleinstein and you and many others.
In the end I'll learn something at least or even produce some usefull results.


It's clear from your results that the MCUs with embedded 16/8 PWM are not the answer as far as I can see, if the FPGA/CPLD implementation with external TCXO it's not absolutely jitter free, I'll do a discrete implementation, there is not very much that I can do for the analogue part with my resources, but I totally don't accept any BS on the digital part, it has to be perfectly synchronized and jitter free.

So yeah, if the couch that I must carry tomorrow (along with other house chores) will leave me some energy, I'll test the  summer/filter/buffer thing with humble TL081, as the couplings are mostly AC and try to see how much is the noise/drift using a fixed set of 2 values: zero and the output of the LM399AH reference. Also a good time to test the dual 18V power supply.

If I can't maintain these two values and this stage drifts or has noise already, then it's no need to bother with PWM dividers and worry about charge injection, the whole base has to be redone with better components until it's statically stable.

 Cheers,
 DC1MC

[branadic]

In my opinion there is no need for CPLD/FPGA. And there is no problem with jitter or other stuff using ATtiny. What you read about is the goal of Andreas to reduce current for use of the circuit as a buffer stage for a portable LTZ1000 reference. Hence he tries different approaches such as sleep mode and smaller clock source to reduce current, with the result of severeal drawbacks.
There's no need to reduce current as much as possible on a DAC device here. I think the circuit could be modified to work as a 8.16 bit PWM DAC directly powered from a 10V reference voltage.

-branadic-

[perdrix]

You'll find a good scan of the 4808 manuals here: https://groups.io/g/Datron-Wavetek/files/Datron%204808

[DC1MC]

You'll find a good scan of the 4808 manuals here: https://groups.io/g/Datron-Wavetek/files/Datron%204808

Thanks, I was missing the AC guy, I hope someone will upload schematics for the DC ones in a bit of a higher resolution, even if one member send me a bit better one it still strain your eyes to look on the schematics details.

EDIT: Holly crap  , it's worth reading the sticky post of the forum, I've got a newer version of the PWM schematic with EXCELLENT quality in the aptly named  file:

https://doc.xdevs.com/docs/Datron/4910_4911/4910%20c20090120%20%5B8%5D.pdf


 Cheers,
 DC1MC

[Kleinstein]

I see no problem with a PWM signal from an µC. It would help to have hardware to support at least 16 bit PWM. I see no real advantage in using an CPLD or FPGA - it's more of a problem in having low level logic signals that might need extra level shifter. In both cases (µC or FPGA) one could consider external flipflops for synchronization. However chances are they are not really needed of the supply to the µC/FPGA is clean.
Other than one simple sync stage discrete logic would be more of a problem. I see no need for an TCXO - a normal crystal clock is well good enough for PWM. It's more about a clean supply.

To get a very high resolution, like more than 20 Bits, there are mainly 3 options, that could be combined in some areas:
1)  2 PWM stages for coarse and fine part to get the extra resolution, after adjustment of the fine stage. This is what the Datron 4910/Fluke5700 do.
2)  Super high resolution PWM from some special µC with kind of analog timing interpolation (timing resolution better than ns)
     Some µC offer this, to directly get PWM with an effective base frequency in the GHz range, though the real clock lower. 
3)  good resolution PWM (e.g. 16 Bit) and additional SD like modulation to keep the contend at the lowest frequencies small.
    This still needs a reasonably high clock.
 
The PWM stages from the Datron 4910 and the Fluke5700 like circuit discussed before are different. The Datron one goes for very low R_on and good matching. The Fluke solution goes for compensation of different R_on with additional circuit. In my few the Fluke way may be easier. The difficulty in the Datron circuit could be hidden in keeping the supply clean.
Just the simple PWM with an DG419 would probably have limited linearity, due to R_on differences.

[branadic]

Just the simple PWM with an DG419 would probably have limited linearity, due to R_on differences.

Chances are good that the difference between both switches are not that hugh. However, we can check that on a few samples I have on my desk.

-branadic-

[Kleinstein]

Linearity can be quite sensitive to the R_on values. One has to compare R_on difference with the resistor for the RC filter. So it only takes something like 1 Ohms to get a few ppm of INL error with a 50-100 K resistor at the filter. Specs for the DG419 are less than about 5 Ohms difference - with a suitable supply it can be better if the extreme ends are avoided.

[DC1MC]

Linearity can be quite sensitive to the R_on values. One has to compare R_on difference with the resistor for the RC filter. So it only takes something like 1 Ohms to get a few ppm of INL error with a 50-100 K resistor at the filter. Specs for the DG419 are less than about 5 Ohms difference - with a suitable supply it can be better if the extreme ends are avoided.

Is this source of INL possible to be compensated with some look-up table or formula, as much as it's beautiful to have 10uV/bit all the time, the MCU power is quite a bit more nowadays.
Also I did some anemic tests and indeed on the very low values the linearity it's really bad. Is there any way to get over this, do we need to have some kind of offset or use different polarity references per switch, one injecting positve voltage and one injecting negative. Sorry for the naive stuff, but I'm really curious what it's actually done for small values around 10-50mV.

 Cheers,
 DC1MC

 

[2N3055]

AOIP SN 8310 (Omega CL8300) actually goes from -10% to 100%. So on 10V range it goes from -1V to 10V, with zero and full scale calibrated in.

[DC1MC]

AOIP SN 8310 (Omega CL8300) actually goes from -10% to 100%. So on 10V range it goes from -1V to 10V, with zero and full scale calibrated in.

Wow, that is really an obscure device, no schematics that I can find.

[Kleinstein]

One may be able to do some numerical corrections, if the INL is accurately measured. I would consider the Fluke type analog compensation of R_on differences more practical. This reduces the current through the switches and thus may reduce the expected INL effect or R_on differences by something like a factor or 100 maybe a little more.

The Datron circuit uses JFETs (J106) with < 6 Ohms resistance and thus likely better matching, especially if selected pairs are used.

[2N3055]

AOIP SN 8310 (Omega CL8300) actually goes from -10% to 100%. So on 10V range it goes from -1V to 10V, with zero and full scale calibrated in.

Wow, that is really an obscure device, no schematics that I can find.

No schematics..
It uses pretty much this principle, it has 2 DG419 doing PWM (lo res and high res), coming from MCU buffered through HCT logic . Input ref is -1 to +9V, output from filter is -0,7 to +7V.  That goes to output amplifier that does voltage scaling and in current mode switches in CC source using same reference. All points are calibrated from software.
Basically same principle.

[DC1MC]

How did they done the shifting ?

[branadic]

AOIP SN 8310 (Omega CL8300)

It's "only" 20ppm accuracy.
Brief Teardown: OMEGA CL8300 (AOIP SN 8310) DC voltage / current standard



-branadic-

[macaba]

I've been working on a PWM DAC design with software correction of linearity, it now has a better linearity than I can measure (my DMM6500 has about 0.7PPM non linearity in the worse region).

It might be of interest to readers here to know that 0.7 ohms of switch mismatch causes 8 PPM of non linearity in my design.

I'm now designing hardware correction of non linearity in an attempt to reduce a 3 point calibration procedure (being performed frequently to accommodate the sensitive-to-temperature variation in the analog switches) to just 2 point calibration (performed less frequently).

Question: Are the Datron 470x, and similar, ~20 million or ~200 million count devices? (i.e. 1uV vs. 100nV LSB)

[Kleinstein]

According to the service manual, the 4708 has some 30 million counts: some 0.6 µV steps with a 0-20 V range.
Anyway the difficult part is the accuracy of the coarse part - The actual final steps size from the fine part is more like a fine detail. Especially now with modern digital electronics and often higher clock speeds, the step size is more like the easy part.

[macaba]

Anyway the difficult part is the accuracy of the coarse part

Makes sense. I've got it easier (maybe harder in some ways!) - I'm generating a single PWM signal for the whole range from a counter with 6GHz effective clock, that is giving me 300Hz PWM with 1uV steps on 20V and is working extremely well.

[Kleinstein]

Doing at the resolution with a single high resolution PWM (e.g. fine timing in some µCs) is possible. However it depends on the accuracy of the chips. Inside a µC there can be nasty interactions, via supply variations and so on that can shift transitions a little. I have seen some odd interactions in my AVR based ADC circuit (e.g. the µC internal ADC clock likely effecting the GPIO pin timing. A more moderate resolution would allow for a separate sync stage based on a flip flop.

I would today get more resolution from the coarse PWM (like 16 bits) and than maybe use a conventional DAC chip for the little fine part.

[perdrix]

You can find the 4808 schematics here: <https://groups.io/g/Datron-Wavetek/files/Datron%204808>

The 4808 is pretty much a better 4708.

David

[Chris56000]

Hi!

I hope it isn't because I might want to build something similar as well!

I'm not bothered about using old 68000 architecture as long as I can filch an EPROM dump for it!

Can anybody offer me a suggested replacement circuit idea for replacing the gas–discharge displays with an LED solution?

Chris Williams

[TheDefpom]

Hi!

I hope it isn't because I might want to build something similar as well!

I'm not bothered about using old 68000 architecture as long as I can filch an EPROM dump for it!

Can anybody offer me a suggested replacement circuit idea for replacing the gas–discharge displays with an LED solution?

Chris Williams

I designed some led display modules to replace the broken displays of a 1062 (which is the same display), these modules run from standard LED drive voltages as I modified my display driver board to be sourced from 5V instead of 180V.

I did a 4 part video series on a 1062 (I also covered the reverse engineering and design requirements in a live stream just prior to those videos)

[dmderev]

Hi,

I know that the discussion is old, but is there anybody who could share the experience on the following:

1. What are the advantages or drawbacks of using inherently linear sigma-delta DAC like 20 bit DAC1220 vs PWM if I were to design the calibrator today? Is it larger voltage levels (10V vs 2V) and drifts which can make a difference?

2. Is the advantage of PWM that it does not need to be calibrated in midpoints and therefore acts like a infinitely accurate voltage divider?

3. Any notes on long-term stability of sigma-delta DACs and the need to keep both reference and DAC in thermally controlled enclosure (oven)?

4. Isn't it more feasible to use an integrated ~12bit DAC as a fine tuning controls for MSB instead of PWM?

5. I could use thin film R2R resistor array as first 10-12 bits DAC, this should probably get good long-term stability, and then followed by fine-resolution DAC like DAC7880 (it is old fashioned laser trimmed 10V MDAC). Could I achieve same or better accuracy as the mentioned calibrators (assuming that I measure the output value of each MSB bit and digitally compensate for mismatch)?

6. Any experience with long-term stability of integrated DACs as sources of calibrated programmable voltage? I.e. long term drift in case of laser trimmed resistive DACs vs modern current-steering DACs?

Thanks!
 

[Kleinstein]

The Sigma delta DACs have limitations to the linearity. It's similar effect as with a PWM DAC and ADCs.  One part is the switch resistance that can be nonlinear and voltage dependent. Another class of problems is from dynamic effects on switching (e.g. voltage dependent charge injection). The SD DACs use very fast switching and is thus more sensitive to those switching effects. Some also use a variable switching frequency, depending on the input code. So the charge injection directly contributes to the output.

The switching effects are temperature dependent and may also change over time. So a stable temperature may be a good idea, but it depends on the chips if really needed.

It is very feasible and in my oppinion a good idea to have a more normal DAC for the fine part together with PWM for the coarse part.  What I don't like on using 2 x PWM is the possibility to interference between the 2 parts, if they use the same clock and maybe even the same frequency. As filter is already there, PWM is of cause simple. So using a DAC chip instead is not a simplification, but more extra caution.

The PWM DAC is especially linear in the central part, if the switch resistors are matched or compensated. If not, one has a square law contribution and needs an extra adjustment at the mid point ( correction term or use the mid point to trim the switch resistance).
A big plus for the PWM DAC is that the long term stability is expected to be relatively good, especially with compensation of the switch resistance.

R2R resistor arrays alone don't make a very stable DAC. Part of the problem are the switches. There are some discrete implematations of rather stable R2R type DACs for a calibrator, but this needs quite some effort, e.g. with low resistance FET switches and wire wound / BMF resistors and trimmers.