HPM7177 ADC from CERN

[jaromir]

Not sure if this was discussed before, but CERN released some fresh details of one of their projects - HPM7177 ADC, including preliminary testing and paper comparing commercially available on-chip ADCs. As name suggests, this one is built around AD7177. I can see some unclear points there, but overall it's nice design with a few details to take inspiration from.

https://www.ohwr.org/project/opt-adc-10k-32b-1cha/wikis/home

[niner_007]

Correct me if I’m wrong, but this is not really an ADC, but more like a DAQ system, they are using an off the shelf ADC

[guenthert]

 Perhaps noteworthy is that their claimed INL error specs are lower than the published one of the ADC.  Did CERN find that AD is overly conservative, are those selected parts or do they some post-acquisition data transformation?

[Kleinstein]

The actual INL can be effected by the input and reference buffering. They may have improved there over the AD reference design used for the DS.
Another point is using a nominal range that does not extend all the way to the extremes. Much of the INL looks like to be similar to an U³ part and there it helps to reduce the range a little and get some extra over-range where the INL is larger.

Driving the differential signal to the ADC is a main part of the circuit. Some of the INL error seen by AD could also come from this part and not just the ADC itself. The extra scaling (e.g. 7V from LTZ to some 5 V ref for the ADC chip and +-10/13 V input signal to a +-5 V range differential signal is quite some effort with likely custom resistor arrays.
 
It looks like they tested only few samples - they could have been lucky.
There can also be some selection check, to through out bad units.

[jaromir]

Perhaps noteworthy is that their claimed INL error specs are lower than the published one of the ADC.  Did CERN find that AD is overly conservative, are those selected parts or do they some post-acquisition data transformation?

They are selecting both ADCs and LTZ references (hundreds of pieces of HPM7177 to be built) to achieve needed parameters.

[DaJMasta]

There can also be some selection check, to through out bad units.

But every device operating in a class near than this is hand-selected (or at least, machine selected based on testing) based off performance, right?  That seems like a given to me.



23 effective bits at 10kS/s is really impressive.  Even if it's a complete module/system with some arbitrary pricetag, getting something like that outside of cryo conditions sounds like we could have some neat additions to the next generation of equipment's highest end.

[Castorp]

Hi guys,

I'm newly registered here, but I've been reading posts for a long time. Now there's finally a good excuse to dive in - I'm the developer of HPM7177 

We do plan to select LTZ1000s for low 1/f noise. We also do burn-in to accelerate their ageing. That was already done for LTZs used in the older digitizer, which is a 3rd order, single-bit Sigma-Delta built of op amps and discrete parts. These devices have been in use in the LHC for over a decade already.

About the INL - Kleinstein is right. It's better than the AD7177-2 datasheet spec because we use part of the range. The driving of the inputs and the Vref pins is also quite critical. It seems that half of the INL curve is very repeatable - it looks the same for those 4 tested "full prototypes", but I've measured something similar on earlier test boards. Luckily, for our most demanding application we only need unipolar range. The digitizer is still bipolar, because it will be used also in another (lower) accuracy class for magnets powered with bipolar current.

So far the plan is not to select ADC chips for good INL. Noise seems to be very much repeatable (both white and 1/f at zero). The temperature controller brings T drift down to pretty low levels. And in any case, the devices in the highest accuracy class are placed in temperature-controlled racks, so normally they shouldn't see more than 0.5 degree delta T.

I'm planning to add a lot more information in the OHWR wiki page. Also, the design documentation will be updated. There are a few small things to polish up here and there.

I'll be happy to answer all sorts of questions. Criticism is also welcome 

Cheers,
Nikolai

[jaromir]

Oh, it's great to see you here.

We do plan to select LTZ1000s for low 1/f noise. We also do burn-in to accelerate their ageing.

This is interesting - how is the burn-in procedure performed?

[Kleinstein]

The noise performance is impressive. If my calculation is right the SNR of the ADC alone is about a 6-9 dB better than the 3458. With the extra noise from scaling the module noise is still slightly better. However there are also limitations: there is some 1/f noise with a cross over at around 0.01 Hz and there may be variations in the gain factor, not only from temperature, but also from random effects (maybe EMI). The other point is that the INL is good but still possibly a weak point, especially for slower conversions.

With the classical multi-slope ADC in the 3458 one has to expect higher INL errors for faster conversions - I would expect more like ~ 10 ppm INL for the 3458 at 10 kSPS. The fast mode does not look like high linearity, but even just going from 10 PLC to 1 PLC amplifies some INL contributions.

For the performance they also need critical resistor array(s) - possibly the most expensive part of the module.

[TiN]

Castorp
Welcome to the forum. It's great to see actual practical high-performance ADC and LTZ1000 reference use. Many of us here playing with LTZ-based refs just for hobby purposes only. I looked at HPM7177 back when it was just few documents and preliminary initial test module results and even picked few pieces from that design into my own experiment but with ADS1262. Also would be cool to hear about bias currents from such a design, if that was validated and tested in detail as well?

One of the questions - Looked on schematics again, but couldn't find the part that used to drive TEC. It would be particulary interesting to hear about temperature stability validation and if there were any issues with induced noise/EMI from running high-power TEC element next to highly sensitive analog circuit.

I have developed few small benchtop TEC setups using off the shelf PID controller (Keithley 2510 or ILX 5910B) to evaluate temperature stability of the various LTZ1000 designs, precision resistors. But never tried to use TEC as onboard thermostat yet, however it would be a good idea for those looking at best possible stability without spending hundeds of hours to select references, chips and resistors for lowest TC.

Also do you get 20-30 week leadtimes for those beautiful custom CerDIP VPG networks, or sourcing BMF resistors is actually better for CERN than individuals like myself? Over last 9 years I had placed few orders (50-100pcs each) for VPG resistors and everytime customer support was rock bottom bad, even without considering money paid. If you can't comment on this, I'd understand, just curious to hear the difference.

[Berni]

Oh neat, didn't know you can just download the entire Altium Designer project and everythyng.

But yeah its just a LTZ1000 reference an AD7177 ADC and some analog front end stuff put together. Still interesting to look at tho.

[Castorp]

I tested some of the Linear SAR ADCs, and they all had considerably higher 1/f noise than AD7177-2:



Those are measurements taken under completely identical conditions: shorted inputs, stable temperature, Vref from a 10 V standard.

I didn't test the LTC2508-32, because I thought it was just like the 24-bit one, but with built-in digital filters. Actually, we use the LTC2378-20 in another digitizer. We do the filtering and decimation externally in an FPGA. The digitizer itself is not a standalone unit like the HPM7177. It's a mezzanine board that plugs into an over-crowded controller. It's very widely used for lower accuracy applications.

HPM7177 is definitely less noisy than the 3458A, but I don't have the exact numbers at the moment.

INL is not our toughest spec, because in the end we don't really deal with dynamic signals. For us it's always about measuring a slowish ramp, and then some DC level which may or may not be around the full scale. In a way, absolute accuracy is also not very important, as the machine operators fine-tune each powering circuit based on the feedback they get from beam measurements. We care mostly about the short- and mid-term stability of our measurement.

EMI is a big concern here, that's why we take good care. For instance, for some 2 kA corrector magnet supplies, the digitizers would be sitting in the power converter rack. That means kiloamps switching not so far, plus big fans and other unpleasant neighbours. I should soon book some time for EMC-testing the HPM7177 together with another system. We have a good EMC lab here.

The resistor networks are not super special, compared to the other stuff we buy from Vishay  I checked - last time I paid <$100 per unit for 25 of them. There are 2 arrays on each ADC mezzanine board, so that's probably about 1/5 to 1/4 of the material cost for the entire digitizer.

The driver for the TEC is not in this unit. It will be in the power supply. I decided to keep them separate - first of all, to keep some of the heat and EMI away, and to make this whole thing easier to debug/manufacture/maintain. Our old digitizer is an "all in one" box and it's just pain.

For now I don't have a release version of the PSU, but I have a working prototype. I'm waiting for an ambient temperature spec from the power converter colleagues before I settle on the final design. What I'm using now is a simple linear voltage-current converter. The setting voltage comes from the HPM7177. It's just filtered PWM from the FPGA. What comes back to the TEC is bipolar current, 1A/1V.

About the burn-in - we do it for 3-4 weeks by stepping the temperature between 80 and 120 degrees C. It's done in a very simple way - the units sit in an oven at 80 degrees, and we switch on and off their heaters to add those 40 degrees. The cycle lasts a few hours, if I remember correctly. The recipe comes from John Pickering (Metron Designs, ex-Datron). Ideally it should be done like this:
https://patents.google.com/patent/US5369245A/en

The voltage reference sub-circuit of HPM7177 (excluding the division down to 5 V) also comes from John. It's basically the same circuit that was used in the old digitizer.

[TiN]

About the burn-in - we do it for 3-4 weeks by stepping the temperature between 80 and 120 degrees C.

Do you have control unit reference without burn-in, to check how does this thermal cycling procedure actually affects reference stability?

[dietert1]

Temperature cycling as proposed by Pickering lasts about two hours. At least the text mentions 15 * 500 = 7500 seconds. The method mentioned above (1 month or so) appears to be something else.

Regards, Dieter

PS: As far as i understand, Mr. Pickering wanted the circuit implemented into the reference board, in order to execute the two hour initialization each time the reference gets turned on.

[RandallMcRee]

3roomlab:

i also tried averaging 1/f noise using ALAnoise, it also seem like 1/f can be made smaller repeatedly with different sample batches 1k 4k 10k samples etc. the rate of "change" of 1/f in averaging is lesser than white noise (as far as i could see in spreadsheet), but they are still doable it seems. 1/f rate of noise reduction is 1/2 of white 

You can't average away 1/f noise! It's not gaussian, unlike white noise.

https://www.eevblog.com/forum/metrology/should-the-number-of-measurements-be-included-in-the-measurement-uncertainty/msg2868714/#msg2868714

 "Low Noise Electronic Design" by Motchenbacher & Connolly:

"A fact to remember concerning a 1/f noise-limited dc amplifier is that
measurement accuracy cannot be improved by increasing the length of the
measuring time. In contrast, when measuring white noise, the accuracy
increases as the square root of the measuring time."

You can find other sources as well, e.g. "Signal Recovery from Noise" by Wilmshurst.

[Andreas]

EMI is a big concern here, that's why we take good care.

Hello,

So I am wondering why you dont use a capacitor between base and emitter of temperature sensing transistor of the LTZ like in the datron design.

See also what I call C11 in my schematic:
https://www.eevblog.com/forum/metrology/emi-measurements-of-a-volt-nut/?action=dlattach;attach=886392

After my measurements this is the most sensitive pin in the whole cirquit.

After I have recognized that the metal housing of the LTZ is connected to the substrate of the chip, but to no other pin directly, I am thinking about wether a additional metal shield around the LTZ can also bring some improvement.

with best regards

Andreas

[Castorp]

I haven't tried measuring long-term drift with and without burn-in. Sounds like a very tedious thing to do 

As far as I know, both methods come from John Pickering. The one with decreasing amplitude seems like a better way to get rid of thermal hysteresis effects mediated by mechanical stress in the package and the leads. Still, the main goal is to relieve the tension in the epoxy that fixes the die to the package. I really don't know whether it's better to do it quickly or slowly.

1/f noise is Gaussian, in the sense that it has Gaussian PDF. However, you can't decrease its variance by averaging when you're dealing with a fixed number of samples. Let's say you have 1000 samples taken at 100 SPS, completely in the 1/f region. That means you're looking at 3 frequency decades of 1/f noise. Now, if you downsample by factor of 10, you have 10 SPS. You have narrowed your BW by a decade - you now have 100 samples and you're looking at 2 decades of 1/f noise. Your variance will be sqrt(3/2) lower because you've thrown away one decade. However, if you take a 10 times longer record, you push one decade down in frequency, you get your 1000 samples again (now at 10 SPS), and you're back at your initial variance. There's equal noise power per log(f), no matter if that's a decade or octave or another base. It's easy to see this in an Allan variance plot, where 1/f is a flat line.

From top of my head, I measured the SAR ADCs sampling at 1 MSPS. When it comes to broadband white noise, their behaviour is pretty straightforward. There's a fixed rms noise value, so you get the lowest density when you run at the highest sampling rate. In other words, you spread this noise over a wider bandwidth. I guess that's the kT/C noise of the sampling capacitor spread over a very wide bandwidth, which aliases multiple times in the Nyquist band. I just checked the datasheet of LTC2378-20 - it states a -3 dB analog bandwidth of 34 MHz. That's way over the maximum sampling rate.

The behaviour of the Sigma-Delta ADCs is pretty different. There you typically don't have much control over the operation of the modulator. The digital filter is there mostly to remove the high out-of-band quantization noise. In between the quantization noise at high frequencies (which rises at N*20 dB/dec, where N is the modulator order) and the 1/f noise at low frequencies (rising at 10 dB/dec), there's a mid-band where the noise floor is flat. That's where you'll see "best noise performance", if you look in terms of noise density. But of course, that's not the full story. If you extrapolate from there, you're likely to get overly optimistic LF noise estimates.

I encountered the many problems of trying to pull this information from datasheets when I produced Fig. 2 in the 2018 I2MTC paper:
https://www.researchgate.net/publication/325285614_Analog-to-digital_conversion_beyond_20_bits_Applications_architectures_state_of_the_art_limitations_and_future_prospects


Edit: I corrected the sqrt(3). If you go from 3 decades to 2, it's sqrt(3/2). The sqrt(3) improvement would be if you throw away 2 decades and you remain with 1. In the end, it doesn't matter where these decades are. It's the same rms noise from 0.1 to 1 Hz, then from 1 to 10 Hz, etc... as long as it's all in the 1/f region.

[splin]

Why aren't you using the AD7175-2?

I'm pretty sure it's exactly the same chip apart from some pointless, but expensive tweeks to the digital filter to produce an 8 extra bits of additional random noise. The noise performance specs are identical for 10kSPS and below (and not surprisingly, not specified for the the 7177-2 for higher rates).

[splin]

Perhaps noteworthy is that their claimed INL error specs are lower than the published one of the ADC.  Did CERN find that AD is overly conservative, are those selected parts or do they some post-acquisition data transformation?

They are selecting both ADCs and LTZ references (hundreds of pieces of HPM7177 to be built) to achieve needed parameters.

Perhaps you'd like to repeat after me: "I'm sorry but I was talking complete b***ocks. Please accept my sincere apologies for attempting to mislead readers here that I had any sort of inside imformation. I didn't, and was simply conjecturing without disclosing that fact. I apologise to anyone that I mislead as a result".

[TiN]

splin
Good one.

Also thermocycling receipe used by John in Datron/Wavetek and later renamed into Fluke reference was NOT few hours, but 8.5 hours. But that's outside of the topic here, so let's keep it civil.

[Castorp]

well i guess i was in the right ballpark to sort the ADC from a noise/samples point of view
if i use the 7177 @ 1k SPS (0.56uV), it is equiv to the 2380 @ 2k SPS (0.52uV) with what looks like a disadvantage in 1/f from the plot, but 2380 is more expensive $$$. so this is where 2508 enters, it would be both cheaper and lower in noise (1k SPS 0.28uV).

Yeah, I think they are pretty similar in terms of white noise. But at 1 KSPS you wouldn't get almost any 1/f conribution. It really starts to play a role if you downsample a lot and you get to the sub-Hz frequencies. That's for the AD7177. For 2508 I expect it's somehow higher (but you still have to be way down in frequency).

Why aren't you using the AD7175-2?

I'm pretty sure it's exactly the same chip apart from some pointless, but expensive tweeks to the digital filter to produce an 8 extra bits of additional random noise. The noise performance specs are identical for 10kSPS and below (and not surprisingly, not specified for the the 7177-2 for higher rates).

Yes, I agree - it's the same chip with minor differences in the digital filters. Indeed, at 10 KSPS those extra 8 bits are pure noise. Even a few of the higher bits are noise. I vaguely remember that 3 years ago I couldn't obtain 7175 for some reason. In any case, for our purposes 10 KSPS is more than enough.

By the way, AD7176-2 has the same Sigma-Delta modulator, but a different input section with much worse INL and much higher 1/f noise.

[iMo]

Happy to see that building an ADC with "comparable parameters" to 3458A with SD (or SAR) chips is doable. The usage of monolithic ADCs has been discussed here many times, except TiN's measurements with ADS1263 this is, imho, the first practical example it is doable.. 

[Castorp]

The INL is not as good of course, but as I mentioned earlier - luckily it's not the biggest concern for our application.

Yesterday someone asked me about the Vishay arrays and I checked my last order. Actually, the lead time was not so bad - it was 10 weeks. The 6-month lead time was for another item, a VHD200 divider. We use those in the older digitizer. We buy them as tempco-matched pairs, so they also cost quite a bit of extra $$$.

[ScoobyDoo]

Hello Castorp - I have a question (concern) about these Vishay array networks ... - there are certain advantages that speak in favor (CDIP - hermetically sealed) of these 144X series, however these consist of individual resistor elements - it is not a single chip array. So did you check Zero TC ratio matching is as good (or better) than the thin film arrays as used in Datron series ? In order to create a stable ratio divider is a thin film array not better than multi-chip foil technology ?  I hope Vishay uses dry and Nitrogen fill before sealing - something to think about ...

Herzliche Grüße/Meilleures salutations/Best regards
ScoobyDoo

[Castorp]

EMI is a big concern here, that's why we take good care.

Hello,

So I am wondering why you dont use a capacitor between base and emitter of temperature sensing transistor of the LTZ like in the datron design.

See also what I call C11 in my schematic:
https://www.eevblog.com/forum/metrology/emi-measurements-of-a-volt-nut/?action=dlattach;attach=886392

After my measurements this is the most sensitive pin in the whole cirquit.

After I have recognized that the metal housing of the LTZ is connected to the substrate of the chip, but to no other pin directly, I am thinking about wether a additional metal shield around the LTZ can also bring some improvement.

with best regards

Andreas

Thanks for the tip, Andreas! I must admit - I haven't considered that issue. When I was talking about EMI and being super careful about it, I mostly meant how we deal with it on the system level. All this stuff with optic fibres, floating GND, transmitting the voltages differentially (even though they are always GND-referenced at the source), the multiple shields, etc.

Hello Castorp - I have a question (concern) about these Vishay array networks ... - there are certain advantages that speak in favor (CDIP - hermetically sealed) of these 144X series, however these consist of individual resistor elements - it is not a single chip array. So did you check Zero TC ratio matching is as good (or better) than the film arrays as used in Wavetek 7000 series (TDP1603 and alike) ? In order to create a stable ratio divider is a thin film array not better than multi-chip foil technology ?  I hope Vishay uses dry and Nitrogen fill before sealing - something to think about ...

Herzliche Grüße/Meilleures salutations/Best regards
ScoobyDoo

ScoobyDoo - you're right, the chips inside are separate. The bulk metal foil types are either V5X5 or V15X5. Perhaps I should finally Dremel into a broken array to see which type I've got. Anyway - so far they're all within the TCR tracking spec, which is 1 ppm/K for all elements. It should be possible to do significantly better using TaN, but for us 1 ppm is good enough since we apply brute force (temperature regulation). We need the temperature regulation in any case, since the ADC gain drift is never going to be good enough.