It is well possible that this are the DNL limitations:
The DAC11001 data-sheet gives a typical (with respect to the codes used) DNL error of some 0.1 LSB or 0.1 ppm (with 20 bit resolution). With a 10 V full scale range this would be around 1 µV.
So the observed steps are about what is to be expected.
The interface of the high resolution DACs is seriell and the digital interference would thus be faster. In addition the main part with digital interference would be capacitive coupling and thus more very fast spikes well beyound the BW of the test. If not carefulll with the software, the INL correction could result in some steps getting twice as large, using 2 LSB jumps. The current observed steps however are smaller, more like 0.1 or 0.15 LSB.
Some lag / rounding is expected from some analog low pass filtering after the DAC. Not sure how much filtering is present in the test.
A ramp of 1 mV/s is relatively slow. With a 10 V full scale range this would allow a 3 hours ramp and this a quite long averaging time. If one does not need the full 3 hours time window, one could divide down the voltage signal and run the DAC with a faster ramp. For testing the slow ramp is of cause a good idea.
The instruments to measure pA range currents are usually not very fast and would average over much of the modulation on top. So the jagged curve is not a real problem, more a sign that the amplifier to test it is good.