There are several mechanisms that can contribute to the INL, some of them are likely negligible. The main INL sources I know are:
1) heating of the resistor at the integrator input. This gives a contribution proportional to the resistor TC (or TC match if tight coupled) and U³. With resistor arrays there can be also a U² part, but the AZ mode will suppress most of this.
2) DA in the capacitor hides part of the charge and gives it back in the next conversion. The slow part of the DA follows the average integrator voltage.
3) Switching the reference before the integrator input is fully settled gives a small error due to the input voltage of the integrator. Luckily with the simple 1 test per period mode for the run-up, the number of short reference pulses is proportional to the input voltage. So the error would be a linear step function, so that only the error from single steps would be real INL. The rest would be just a slight change in gain.
4) Having two short phases close together could have some additional effect, e.g. with the 4053 supply not settled or a tiny rest at the integrator. This case happens more often near zero and less frequent at the extremes. This effect is expected to give some u² or similar dependence, if visible at all. Longer time for the short phase should reduce this effect.
5) The settling of the integrator can depend on the current the OP drives. The OPs GBW or phase reserve seems to depend on the output current. As the settling part can contribute to a small offset to the integrator input, this effect can contribute to INL. The effect on the settling is visible on the scope and the extra current mirror can to a large part suppress it - however with no visible effect on the INL. So this mechanism still seemed to be rather linear. A similar effect comes in combination with short pulses, as the effect of a short pulse may depend on the current.
6) leakage on the board, at the resistor array or 4053 can couple the input voltage a little to one of the references. This would give a U² contribution, as the time that reference is used depends linear on the input.
7) there can be some coupling from the input buffer / input to the integrator to the reference circuit. This can be thermal or through the ground or maybe the supply.
8 ) The buffer may still be not perfect, even with using a bootstrapped supply. Load the output was one such effect, that was visible before adding a bias.
9) some couplings, e.g. from the comparator / slope amplifier to the clock. This was a problem before using the canned oscillator.
Together with the extra sync FF this effect should be minimal.
10) if only a 1 OP integrator is used, the residual voltage at the input in combination with mismatch of the resistors can cause an error.
The 2nd OP in the integrator should suppress this part to a large part. With the resistor arrays the mismatch is relatively small and a 1 OP integrator may be possible.
11) thermal coupling in the 4053. Due to the low resistance the power is small, but there still is some heat.
12) During the transients there can be a small current at the OP inputs at the integrator. Though JFET OPs the ones used have protection diodes that can start conducting over some100 mV. This is better than with BJT based OP that can start to have more current beyond some 40 mV, when the input stage starts to become nonlinear.
13) The fast part of the DA depends on the very end of the run-up and the charge measured. This can give an more local INL error especially at the steps when the run-up part changes. The fast DA is also visible as some drift of the residual charge, but the effect is usually small with a good cap and some waiting time in the run-down.
Then there are also those effects I still missed and a few more I know, but with very small effect.
Quite a few of the possible INL source are switching related, so that very fast modulation to reduce the DA error is not only positive.
The idea of IC20 (DG419 at the slope amplifier) is to modify the feedback during run-up. During run-up extra signal from the average integrator output is added. This would reduce the average integrator voltage and this way the slow part of the DA, one of the know larger INL sources. This way lower modulation frequencies are possible, with less switching related errors. As an additional side effect there is less loading of the integrator during run-up and the small resistor for low noise is only chosen for the run-down phase, when it is needed. I have not tested this, so just an idea that has a good chance to work. If not, one can still keep the DG419 not populated and change the one resistor at the slope amplifier input.
The current mirror to the integrator output is to keep the output current of the integrator about constant, as it was observed that the current has a visible effect on the OP speed/settling. The current is not constant all the time - there are still the jumps up and down by the reference, but the two level for going up or going down would stay about the same. The additional offset shifts the current to the one side that works better for the OPA172. The improvement of the settling is visible on the scope (see the scope traces a few posts back) - but not much INL effect, even with 20 K at the integrator.
. So the current mirror is optional for a possibly small effect, not yet detectable. Especially with higher resistors at the integrator one could likely skip the current mirror.