A 20x improvement from 1 change, Now that is something very nice to see,
For the canned oscillator graph, how does that look if scaled by PPM of input instead of delta voltage?
The improvement was relative to a bad starting point. So the unusual point was that the the crystal at the µC was unusually sensitive to external effects. The 2nd board is now about to the same level (maybe a little better) I have with the 1 st. I also started with just a crystal on the first board, but there was a relatively small effect changing to the canned oscillator - because of this (and because it took some time to find one) I was so slow in changing to the canned oscillator.
The ADC full scale is at some +-10 V. So the variations of some 2-3 µV in the difference test correspond to some 0.2 -0.3 ppm of the full scale. However this test is not a full INL test: It does not include all INL contributions - mainly DA and switching effects, but not things like self heating of the input resistor and the input buffer. On the other side it is also effected by variations in the 5 V supply effecting the charge injection and a non ideal test signal (e.g. nonlinear capacitance).
Compared to normal ADC / DMMs specs the current state is about the following:
Input range about +11 V to -12.5 V, with some limitations beyond some +-10 V
Sampling rate: 24.5 SPS: 20 ms input, ~250 µs rundown , 20 ms zero (or negative input), ~250 µs rundown
Nominal (numerical) resolution: ~28 bits
Noise: about 900 nV_RMS for the 24 SPS auto zero readings, difference of the 2 readings with 50 K input resistors.
For a DMM this would be called just 7 digit resolution for 1 PLC (24.5 readings/second)
With averaging one would be at 8 digit level for about 100 PLC.
However the LM399 reference adds extra noise with higher measured voltages. So the real resolution is more like 6-7 digits, limited by the reference. The lower noise is still useful at the low end of the range and for internal tests (e.g. ACAL).
Speed wise it is currently 1 PLC and for tests also 2 / 4 / 8 / 16 PLC, but more noise than averaging.
The Hardware should also work reasonable up to some 1000 reading per second with good resolution - currently the data transfer takes longer.
I have not tested the stability / temperature drift very much. The crude test gives some 1 ppm/K for the ADC gain in addition to the LM399 reference (should be < 1-2 ppm/K).
It somewhat depends on the resistor quality, so the spec limit would be more like 10 ppm/K, but the specs on the NOMCA resistors seem to be conservative and TC matching to the 1 ppm/K level seems more like typical.
The difficult part is linearity. Here the measurements are limited:
The turn over error (testes at some 9.3 V and 8.4 V) for both board is at some 3-8 µV, so around 0.5 ppm for each reading.
The wiggly part of the INL (mainly switches and DA) looks like better than some 0.3 ppm.
The thermal effect of the input resistor (U³ part) is expected to be less than 1 ppm FS for the TC seen in the gain drift.
Guaranteed by design is difficult as at that level. The tricky parts are the small effect one does not fully understand or has no good control over (e.g. parasitic coupling, acoustic effects, RF interference, thermal effects, board leakage). So there is no guaranteed by design limit - it is more a best case scenario in the design, from the noise sources and INL effects one understands. This best case scenario is at around 500 nV noise (mainly the 50 K resistors) and ~0.05 ppm INL from the DA (depends on the run-up) and ~ 0.2 ppm INL from the thermal effects of the resistors.