DIY high resolution multi-slope converter

[Rerouter]

Software is kleins, so would be up to him how he wants to host it,

PCB can be, never used it before, as never looked into the whole syncing local to site, and my adventures with bruteforcing on github in the past seemed the wrong method.

A ground plane / fill's role it to make sure there is a nice short return path for all signals, however similar can be accomplished with a ground trace bundled or better wrapped around those signal traces to keep loop areas small,

I could flood fill things, but I'm hesitant to as it both conducts heat better meaning the isolated little islands of heat end up effecting larger areas, and any noise on that plane can couple into traces and pads. you can see the reverse for the resistor arrays and reference where I do want that area at as close to the same temperature (relative to ambient) at all time.

Instead I focused on making those loops as small as possible to accomplish a similar task, sometimes its better to steer the current exactly where you want it, than risk multiple things mixing, and where possible followed the golden rule of power to the decoupling capacitor then to the device where possible.

Tweaking some other small things, practically a review stage, like making sure I can actually source all the parts, finding a good Jfet for the task, all the transistors had the pinout rotated, etc

Edit: LTC2057 is now back to a SOIC, way too pricey in MSOP, Jfet I am looking at is "MMBFJ31DLT1G" as based on datasheet needs more than 15mA to function correctly.

[Kleinstein]

With only 2 layers there is not much left for a ground plane. For the precision DC part I think it is better to have control of the ground and not use a ground plane. It may be OK for the digital part, but there is not that much true digital.  A also agree that more ground fill would not really make things better. 

For the JFETs (LM399 current limit and ref. drive) the MMBF4392 or MMBFJ111 should be OK. The transistors should be just standard small signal NPNs/PNPs, no special needs.
The DG419 should be the normal version, not the DG419L (lower supply limit).

For the OPs there may be a few options to choose from, but all with standard pin-out (no LT1013). It's a question of availability, price and preference for low power consumption. The main performance critical one is U11 where I currently have an OPA1641. The OPA140/141 would be another, maybe more obvious choice.  For the Buffer the OPA145 is used because of low noise at still low power consumption.

I have not experience with github. Maybe I put it there.

[Rerouter]

Ok up on github, anyone who wants to contribute, go nuts,

https://github.com/Rerouter/Multislope-ADC-PCB

[Rerouter]

Mainly cosmetic changes today while I run through the BOM, and adding more test points, mainly around the reference.
An old preference of mine is to put pin-outs on the PCB so diagnosing is easy.

Will keep the op amp options in mind, right now everything is bog standard SOIC, so should be able to flip around freely

[Kleinstein]

I think there could be still some ground loops with the filter caps at the regulators. The ripple current through the caps seems to share some part of the normal ground lines.  So there is chance to see some ripple on the supplies.

For the OPs there are in deed a few options. However in most places there are several good enough options (especially with only a LM399 reference). So there is not much need to test different combinations.
The 2 main critical OPs should be the 2 of the integrator: The slow one needs good low frequency noise (still have the resistors as a competing noise source). The fast one driving the output should have a good output stage and speed - this is the less predictable part, possibly effecting the INL.

[Rerouter]

Power supply ground is on its own little trace back to the power in plug. Is it the current between the regulators your concerned about. Or is the thick ground traces on the top layer hard to tell?

With the fast integrator op amp biased in to class A operation the need for a "good output stage" should be mostly resolved. As there should be little to no changeover in the output stage.

The integrator has left me wondering about capacitive load driving.

Edit: will move the 5V ground to the power connector to keep everything to the same node.

[Kleinstein]

The ground track on the bottom from the AC in looks suspicious: the ground of the filter caps (unreg to GND) can carry some AC current and this can couple to the capacitors at the output. The current is relatively low, but the layout is not that good. That area is not very visible for the top.

The other point I just noticed is the 5 V supply to the 4053: the ground parts is quite a snakes trail. The PSRR for the LV4053 is not as bad as I initially though, but it is still not perfect. The 34401 ADC even has a separate low noise regulation (derived from the main 7 V reference) for the HC4053 chip. With the give relatively long trace, I would consider some optional more local regulation for the 4053.

When driven to class A output the fast integrator may not be as critical, but it is still one of the not so well understood points. Capacitive loading is somewhat linked to the output stage. Those OPs that are relatively tolerant to capacitive loading also tend to have a low open loop output impedance.

There is some capacitive loading, but not too bad: The integrator capacitance is not directly capacitive loading. The inverting input is only a virtual ground no true ground. Things like C17 and R20 are more like helping by adding real impedance. Because of the capacitive loading I currently have C37 unpopulated - more like keep it just in case as other ADCs have it and there may be a reason behind it I have just not yet understood. C14 from the other OP in the integrator kind of couples the 2 OPs - so this could be seen as capacitive load, but it helped with the response, both in real life and the simulation.

[Rerouter]

Ok, how would you prefer the power supply grounds? probably having a slow day, but not clear how exactly you want it handled. "current" was how it was when i posted the last picture, 3 is how I have it at this moment, but happy to flip it about.

Shortened the ground on the 4053 bit, and broke the micro off on to its own 5V feed split right at the regulator.

Also included some board pictures with no silk to hopefully make things easier to tell

[Kleinstein]

I am afraid that non of the suggested layouts for the regulator part is really good. It may still all work OK, as the current is small and this only low low ripple currents. Still it is odd to have this rather basic part not right.

The ground sides of the input filter caps and the outputs should not be mixed. The version 2 may be acceptable if the capacitors for the regulator output side would get there own ground (could be one shared).

From the input side there is input ripple current flowing trough the input caps - the connections in this path should not be reused.
There is no need to have a good ground connection for the AC input.

The ideal circuit with a central ground point is not that practical with so many parts. So one kind of has to compromise a little.
One can see the input side as a separate block, with it's own approximate ground point with the 3 input side caps the link to the input and the one connection to the central ground point for the regulator outputs.

One point that makes it difficult is having the capacitors for the output side also close to the regulators. They can be very well on the other side or more to the center of the board where there is space. The caps don't produce much heat and they don't need the heat from the regulators unless operated well below freezing. The caps on the output side can likely be smaller (e.g. more like 10-100 µF), while the input side caps may need some size (e.g. 220 µF, maybe 470 µF with a more power hungry reference), when using a 50 Hz transformer.  The regulator GND pins are more like inputs, so they may share a single line. So the central ground could be with the output capacitors.

[Rerouter]

Any better? analog and digital 5V right now have a separate feed to the output capacitor, analog also have another point of load cap closer,

Unreg current paths are now seperated out, all output ground current uses the regulator traces, so if the ground moves up and down a little, the regulator will track it.

the 100nF caps current should be almost nothing, so they are sharing the regulator ground for now.

[Kleinstein]

It looks much better. There still seem to be a second ground connection at the 5 V filter cap on the top layer.

[Rerouter]

Clearer? the ground that wraps around the bottom does not actually connect.

[Kleinstein]

I did a few more tests for the turn over error with the integrator resistance still at 10 K. I know that 10 K is too low for the integrator to expect really good performance. This is more like a test under intentionally more difficult conditions to maybe get an idea about the source for INL errors.

In the normal configuration the turn over error follows about the simple square law. So it looks like an additional U² part to cause the turn over error.  for 9.3 V (the current maximum of my test source) the error reaches some 26 µV or some 3 ppm of the voltage.
The turn over error did not change much for 2 PLC mode and for a slower (half the speed) modulation in the run-up. Similar disabling the current mirror has very little effect - in the after-thought this is not such a surprise:
The main effect of the current mirror is to improve the settling at the integrator input and make it less dependent on the current. So the current mirror would reduce a possible effect due to settling of the integrator. Since changing the frequency and thus the number of switching events did not have an effect the settling should not contribute to the turn over error. So no longer such a surprise to no effect from the current mirror. There may still be an effect for the odd powers.

After this I did 2 tests exchanging the 74LC4053 switch chip: the first try was with the classical 74HC4053 (ST brand). This gave a huge turn over error, something like 10-15 times larger.  A main difference is that the on resistance is typically about 4 times higher. So the next try was testing 2 x 74LV4053 in parallel (stacked DIP). This gave a much lower turn over error - nearly too good to be true (-2 µV to 1 µV)  .

With this test, there could still be a chance that 20 K integrator resistance could work.  It looks like there is a problem if the voltage drop the switches gets too large. And switch resistance is an important factor, entering more like a square, not just linear.

Attached is a plot for the turn over error with 1 and 2 x LV4053.

[Kleinstein]

I think I got an idea which effect could cause this nonlinear effect:
The on resistance of the CMOS switches may not be so linear at higher currents. The data-sheets show the R_on changing with the DC-level. In a simplified picture about half ohmic voltage drop on the switch acts as a shift in the DC level and this way causes a nonlinear resistance. From a DS for HC4053 from Phillips I get a change of resistance by about 20% per volt. For 1 mA at 100 Ohms one has 100 mV of drop and could thus expect some 1% change (~ 1 Ohms) in R_ON. This would be 100 ppm of the 10 K at the integrator. The observed error (with the HC4053) is on the order of 60 ppm at 10 V.
 
This type of error would be proportional to the square of the input voltage and the square of the ratio of R_on to resistance at the integrator. This about fits the observed errors.
To get an error less than some 0.1 ppm we want  r_on/R_int less than about 1/1000. This would be some 30 K for the LV4053.

[Rerouter]

Looking over what is available to buy, I guess leaves the question of what ones we can immediatly knock out for there on resistance or similar.

Datasheet	Manufacturer PN	Manufacturer	Price	On resistance max	Channel Matching	Single Supply	Split Supply	On Time, Off Time	Charge Injection	Channel Capacitance CS,CD	Leakage
https://datasheets.maximintegrated.com/en/ds/MAX4051-MAX4053A.pdf	MAX4053ACSE+	Maxim Integrated	3.75	100Ohm	6Ohm (Max)	2V ~ 16V	±2.7V ~ 8V	175ns, 150ns	2pC	2pF, 2pF	100pA
https://datasheets.maximintegrated.com/en/ds/MAX4051-MAX4053A.pdf	MAX4053CSE+	Maxim Integrated	3.58	100Ohm	12Ohm (Max)	2V ~ 16V	±2.7V ~ 8V	175ns, 150ns	2pC	2pF, 2pF	1nA
https://datasheets.maximintegrated.com/en/ds/MAX4617-MAX4619.pdf	MAX4619CSE+	Maxim Integrated	2.24	10Ohm	200mOhm	2V ~ 5.5V	-	15ns, 10ns	3pC	5pF, 8.5pF	1nA
https://datasheets.maximintegrated.com/en/ds/MAX4558-MAX4560.pdf	MAX4560ESE+	Maxim Integrated	5.18	160Ohm	2Ohm	2V ~ 12V	±2V ~ 6V	150ns, 120ns	2.4pC	2pF, 4pF	1nA
https://datasheets.maximintegrated.com/en/ds/MAX4581-MAX4583.pdf	MAX4583CSE+	Maxim Integrated	1.97	80Ohm	1Ohm	2V ~ 12V	±2V ~ 6V	200ns, 100ns	0.5pC	4pF, 6pF	1nA
https://datasheets.maximintegrated.com/en/ds/MAX4581L-MAX4583L.pdf	MAX4583LESE+	Maxim Integrated	2.57	80Ohm	1Ohm	2V ~ 12V	-	200ns, 100ns	0.5pC	4pF, 6pF	2nA
https://assets.nexperia.com/documents/data-sheet/74LV4053.pdf	74LV4053D,118	Nexperia USA Inc.	0.62	105Ohm	2Ohm	1V ~ 6V	-	31ns, 24ns	-	3.5pF	2µA
https://assets.nexperia.com/documents/data-sheet/74HC_HCT4053.pdf	74HC4053D,652	Nexperia USA Inc.	0.44	120Ohm	6Ohm	2V ~ 10V	±1.5V ~ 5V	31ns, 29ns	-	3.5pF	100nA
https://assets.nexperia.com/documents/data-sheet/74HC_HCT4053_Q100.pdf	74HC4053D-Q100,118	Nexperia USA Inc.	0.44	120Ohm	6Ohm	2V ~ 10V	±1.5V ~ 5V	31ns, 29ns	-	3.5pF	100nA
https://assets.nexperia.com/documents/data-sheet/74HC_HCT4053.pdf	74HCT4053D,112	Nexperia USA Inc.	0.48	120Ohm	6Ohm	4.5V ~ 5.5V	±1V ~ 5V	34ns, 31ns	-	3.5pF	100nA
https://assets.nexperia.com/documents/data-sheet/HEF4053B.pdf	HEF4053BT,652	Nexperia USA Inc.	0.44	155Ohm	5Ohm	3V ~ 15V	-	-	-	7.5pF	200nA
http://www.onsemi.com/pub/Collateral/MC74HC4051A-D.PDF	MC74HC4053ADG	ON Semiconductor	0.5	100Ohm	10Ohm	2V ~ 6V	±2V ~ 6V	-	-	50pF	100nA
http://www.onsemi.com/pub/Collateral/MC74VHC4051-D.PDF	MC74VHC4053DR2G	ON Semiconductor	0.6	100Ohm	10Ohm	2V ~ 6V	±2V ~ 6V	-	-	50pF	100nA
http://www.onsemi.com/pub/Collateral/NLAS4053-D.PDF	NLAS4053DR2G	ON Semiconductor	0.71	26Ohm	10Ohm	3V ~ 5V	±3V	23ns, 23ns	12pC	10pF, 10pF	100nA
http://www.onsemi.com/pub/Collateral/MC14051B-D.PDF	MC14053BDR2G	ON Semiconductor	0.43	280Ohm	10Ohm	3V ~ 18V	-	-	-	7.5pF	100nA
https://www.renesas.com/en-us/www/doc/datasheet/isl84051-52-53.pdf	ISL84053IBZ	Renesas Electronics America Inc	1.98	100Ohm	6Ohm (Max)	2V ~ 12V	±2V ~ 6V	50ns, 40ns	2pC	3pF, 9pF	2pA (Typ)
http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd74hc4051	CD74HC4053M	Texas Instruments	0.55	130Ohm	5Ohm	2V ~ 6V	±1V ~ 5V	-	-	8pF	100nA
http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd74hct4051	CD74HCT4053M	Texas Instruments	0.55	130Ohm	5Ohm	4.5V ~ 5.5V	±1V ~ 5V	-	-	5pF, 8pF	100nA
http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd4051b	CD4053BM	Texas Instruments	0.5	240Ohm	5Ohm	3V ~ 20V	±2.5V ~ 9V	-	-	0.2pF, 9pF	100nA
http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd4051b	CD4053BNSR	Texas Instruments	0.46	240Ohm	5Ohm	3V ~ 20V	±2.5V ~ 9V	-	-	0.2pF, 9pF	100nA
http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd4053b-q1	CD4053BQM96G4Q1	Texas Instruments	0.53	240Ohm	5Ohm	3V ~ 20V	±2.5V ~ 9V	-	-	0.2pF, 9pF	100nA
http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fsn74lv4053a	SN74LV4053AD	Texas Instruments	0.59	75Ohm	1.3Ohm	2V ~ 5.5V	-	14ns, 14ns	-	0.5pF, 8.2pF	100nA
https://toshiba.semicon-storage.com/info/docget.jsp?did=54976&prodName=74HC4053D	74HC4053D(BJ)	Toshiba Semiconductor and Storage	0.4	100Ohm	5Ohm (Typ)	2V ~ 6V	-	38ns, 38ns	-	5pF	100nA
https://toshiba.semicon-storage.com/info/docget.jsp?did=54977&prodName=74HCT4053D	74HCT4053D(BJ)	Toshiba Semiconductor and Storage	0.4	110Ohm	5Ohm (Typ)	4.5V ~ 5.5V	-	45ns, 59ns	-	5pF	100nA
http://www.vishay.com/docs/69685/dg4051e.pdf	DG4053EEY-T1-GE3	Vishay Siliconix	1.49	78Ohm	910mOhm	3V ~ 16V	±3V ~ 8V	75ns, 88ns	0.3pC	2pF, 3.1pF	1nA

[Kleinstein]

For the switches, I have tested so far:  LV4053(best),  HC4053(Ti), HC4053(ST), HEF4053 and max 4053. The main chips left that I see for tests are DG4053 and NLAS4053DR2G / VHC4053. Chances are the last two a pretty similar to the LV4053. The DG4053 may be interesting because of a slightly lower speed - not sure if this helps or is a problem.

For the resistance specs it looks there are still some mixed numbers: the DS can use different conditions, like supply and also the DC level. Than it is also the question between maximum and typical.

I consider the LV4053 good enough. At least the ones I have here showed very low leakage and the on resistance is considerably better than the HC4053 version with about the same capacitance and less supply spikes.
The problem can be leakage, as the cheap logic series chips are not really tested for leakage. The specs are at some 100 nA with a typical value in the 1-10 pA range.

With R >= 30 K it looks like on resistance is good enough to get very low INL. 20 K is still a bit borderline but not too bad.

[Rerouter]

Been slowing working through the specs for our specific setup, and agree the DG4053 looks to have the best typical values out of the lot of them, with ones like the HEF4053 seeming downright horrible based on the spec sheet alone.

Also confused about what brand LV4053, as they both seem much faster than the rest, and I was left feeling you preferred slower switches, could there be a chance faster is better?

[Kleinstein]

For the speed of the switches, this is a two sided thing: fast gives the chance to get less jitter and the dead time in between is shorter. However this also gives more of the very high frequencies towards the integrator. Also the supply decoupling is more critical at the higher frequency end. A good point of the LV4053 is also having low power dissipation capacitance and thus low supply spike - so less critical supply decoupling overall.

I have use a Ti Version of the LV4053.
The main weak point of the LV4053 is that the leakage specs (test limits) are not very good. So they are not really tested for leakage - they can still be good: I see very little leakage so far (e.g. 10 pA range for the 3 switches and 2 OPs).

[branadic]

There is an interesting looking source for hermetically sealed PTFE capacitors on ebay, which also offers 2.2nF 500V. You might want to give them a play to see, if they can do any good to your INL as well?

https://www.ebay.de/itm/560pF-0-1uF-500V-K72P-6-PTFE-Capacitors-fits-brand-name-Teflon-USSR-NOS/193107860442

Nothing to loose, as they cost only 0.59€ each.

-branadic-

[Kleinstein]

I thought about these NOS PTFE caps. However they are mechanical quite large and it is not sure they are actually good. I forgot where, but there was a report about not so great performance.

The capacitors I have now (TDK  C0G ceramics) are quite good: about the 5 times lower DA than PP / PS. In the diagram from Bob Pease they are about where the PTFE cap is.  With the extra switch to change the feedback in run-up I see a chance that the error due to DA could be reduced even more by maybe a factor of 5 or so. Currently I don't think the DA is the limiting factor - still lower DA could allow for a slower modulation and this way less effect from switching.

[razvanme]

@Kleinstein, is someone trying to redo the code so it's easier to understand / modify? or are you working on a refactor? If not I can give it a go (without hardware for now), if the board on git is ok for a start, I can make some and test the software on the actual board.

Based on what I understood from the descriptions you provided here and on the other thread, bellow is the actual code that will do the runup. Did I understand that correctly? You used a "before" in some descriptions and that makes me think the comparator reading / check is using a queue of 2 values.

Another patent describes having references either both on or both off for equalizing the number of P/N Ref switching on each slope while the comparator is checked.

Code: [Select]

    RUNUP:
        SWITCH SWITCH_VIN                                           //2 clock cycles
        //----------------- We are counting clocks from here down
        // Clock cycle accurate delay
        DELAY (INTEGRATE_TP/2)-4 // compensate for the next switch
        RUNUP_LOOP:
            SWITCH_TOGGLE SWITCH_TOGGLE_CURRENT, SWITCH_TOGGLE_MASK, SWITCH_VIN   //4 clock cycles
            //-------------------- From here we are integrating VIN + VRP as start
            //  the next loop we are integrating VIN+VRN and toggle on a subsequent loop
            DELAY us_to_cycles(1)-5 // 3 for jmp and 2 for switch
            // If integrator is positive go to the needed slope
            LOOP_IF_POSITIVE 1f                                     //3 clock cycles
       
            // The integrator is negative, we integrate VREFN to go positive
            SWITCH SWITCH_VREF_N | SWITCH_VIN                       //2 clock cycles
            //---------- From here we are integrating VREFN+VIN   
            DELAY us_to_cycles(20)-12
            INCR SLOPE_COUNT_VRN                                    //2 clock cycles
            JUMP_IF IS_ONE(TIFR1, OCF1A), PRERUNDOWN                //4 clock cycles
            rjmp RUNUP_LOOP                                         //2 clock cycles

            // The integrator is positive, we integrate VREFP to go negative
        1:  SWITCH SWITCH_VREF_P | SWITCH_VIN                       //2 clock cycles
            //---------- From here we are integrating VREFP+VIN
            DELAY us_to_cycles(20)-12
            INCR SLOPE_COUNT_VRP                                    //2 clock cycles
            JUMP_IF IS_ONE(TIFR1, OCF1A), PRERUNDOWN                //4 clock cycles
            rjmp RUNUP_LOOP                                         //2 clock cycles
    PRERUNDOWN:
        // When we exit the runup loop we exit with 6 missing clock cycles from a full integration slope period
        //  2 for rjmp and 4 for the new switch toggle, compensate for that in the switch and extra delay
        DELAY 4
        // Make sure we are above 0
        // Integrate -VREF So we go in a positive direction until we go above zero
        SWITCH SWITCH_VREF_N                                        //2 clock cycles
Attached is a full project in AtmelStudio.

PS. It's still WIP. Also the pins do not correspond to the actual board, I just added the defines to make sure everything is working.

[Kleinstein]

The code I uploaded where complete versions, with run-up, run-down and the special test cases to measure the slope ration and ADC scale. The code also includes some dead code no longer needed, especially a 2 nd version for test of the ADC scale.  I do not yet have the code to control the front end - that part is still under development.
There is quite some code beyond the pure ADC conversions to aid testing: via UART control different modes of operation can be selected (integration time 1,2,4 PLC , RU version, loops over different setting of the input MUX, test mode for the ref. ratios, test mode for DA).
The PC side of the code is still essentially the old Turbo pascal version - I have started with a C code version that also runs with an UART-USB converter.

The AVR code is in ASM and not C, as the program run time is used for the delays. So AVR-studio uses an ASM project, not C. Because of the delays it would be very difficult to use C code - depending on the compiler the lenght could vary and especially the UART part with the same run time for different cases would be tricky in C. It already took quite some simulator runs to get it right in ASM.

Other peoples ASM code can be hard to understand, especially with code that has evolved over time, so that some name to the registers don't make much sense in all cases.
I can keep most of the data in the CPU registers that get  names. Only a few "variables" in the SRAM are used.
The stack like UART buffer can be really confusing - for better readability this may be a point to to change to a more normal FIFO like buffer.


In the current version there are 8 different run-up versions to choose from. The main versions  (e.g. from runup_P3f: on ) use a simple 3 phase system, a little like the HP 3458, 34401 and quite some other DMMs. During run-up there is always one reference active - no zero phases in the this version. As pseudo code the procedure is:
1) positive reference for some 12 cycles (varies between RU Versions)
2) depending on the comparator setting (from register t3)
     a) positive ref.  phase of some 78 cycles   (the exact length varies between RU versions)
     b) negative ref. Phase of some 78 cycles
    This includes sending UART data from a buffer if needed,
     counting the positive phases and at the end read the comparator status to register t3
    The exact timing when the comparator is read can vary between versions.
3) negative reference  for some 12 cycles  , and loop to 1) until finished.

There is no queue for the comparator, just a single buffer in a register (t3).

The rundown is similar to the HP3456. First one direction (positive) than the other and than the fine slope (positive) and finally as a new point reading the µC internal ADC with the integrator in hold mode.


The current standing is that I am routing / designing (depends on space) a board for the input part for voltage readings. The chopper type amplifier (a little like the Datron 1281) part at least works on the bread board to the degree expected for the BB.  As a fall back an AZ OP should be possible on the same board.

[razvanme]

I understand all your points. It's hard at first glance to understand the original code that's why I figured it's easier to ask you .
Also I think I was misunderstood, the snipped above is actual code from the project, in ASM using macros to simulate 'high level', the comments next to a line are the number of clock cycles that macro takes regardless of compiler since it's actual ASM ( actually regardless of compiler version / flags or other code ). I am aware timing is critical and at least the runup / rundown must be done in ASM. The only C part is main and eventually processing of UART commands since that is not critical. Also there are no variables, everything is in registers (we have a lot of them), 0 SRAM occupied for code that actually does something, it's a first for me anyway. I don't think it's that hard to read the above extract ( I am aware it might not be easy for others especially if you switch from another project or mental model of the functionality / project layout ).

So I guess the answer is no for now. Roger that.

[Kleinstein]

The mix with macros is really hard to read, if one is not familiar with the macros.
The macros may be nice for a simulation, but one step more tricky than pure ASM.

The run-up - method described looks a little different from my solution. There seem to be a phase without a reference instead of the positive + negative phases as a sequence.  Not sure if it really works as I don't see if the total number of switching events is constant.

[razvanme]

It's a bit differently laid out I agree.
 Toggle VREP or VREFN for 1 us
     Integrate depending on comparator
  Jump to toggle

Now that you mention it, it might get out early and not finish a full P+N,based on your steps the timeout for 20ms should be checked at the end of the 3rd step before jumping to 1. That way it's sure to have a P + N per full cycle. Got it. There is no phase without reference applied, again I do agree it's hard to decode someone else's code if that's not a priority or there is something else that require's one's attention .

Anyway I don't want to take over the thread with software discussions if that is not an objective now. I just wanted to know what's the status of the software and if I can help.

Will keep following the hardware development .

Thank you.