DIY high resolution multi-slope converter

[Kleinstein]

The exact timing of the ADC start is not that important. At least with a low bias OP there is not much drift in the hold state. I see about 3 LSB (with 133 LSB corresponding to 250 ns of the slow slope or some 12 ns of the -13.3 V reference) of drift over the time for 2 conversions (a little more than 100 µs). So an uncertainty of some 4 µs is not a real problem.
If really needed, one could start the ADC from a could start (e.g. ADC off during the end of run-up) thus would give a reading some 56 µs or/and some 110 µs from the start.

The waveform shown looks a little better than what I got without C17/R20. With the give C17/R20 and OPs there is a peak, but only little overshoot. So I think a had some luck finding good values with just my 3rd tries. The OP models may not be that accurate in all respects. For the very fast part the open loop output impedance could have some effect - so the TLE2071 may behave quite different from an OPA172, despite of similar GBW. Different OPs (the precision OP is less critical) may need different compensation. Another point can be the switches - LTspice is know not to accurately model switch charge injection. The Ferrite beads I use now are 300 Ohms - my first try after THT types with no data.
Anyway measuring at the integrator input can be tricky - the probe might effect the settling. For this reason i have the test point (LSP6) at the output of IC11 (currently OPA1641) that also shows the settling (as a square wave - more or less the integral of the peak at the integrator input), but with much less sensitivity to load.

[Kleinstein]

A few more tests on the ADc circuit:

To get even lower noise I added resistors in parallel to the integrator input (R1,R2,R3), now with 2x 50 K in parallel. The Integration cap is increased to some 3.2 nF to stay in range. This comes at the price of possibly higher INL error, but for an linearity test less noise and more INL is a good thing.
The INL test is like before, using 2 different run-up versions, one with 40 kHz modulation and one with 120 kHz modulation to measure the same slowly varying voltage. This is a test mainly for the shorter range INL errors, like errors in the slow slope contribution or switching artifacts.

The first 2 graphs show the data for the linearity test. Each point is from the average of 25 conversions of 40 ms each. So slower conversion and thus less noise.  The result looks promising: the more periodic part is likely to a large part (> 2/3) from the faster mode, that also uses rather short switching times. For the longer range drop one has deviations of some 1 µV so something around 0.1 ppm FS. Here it's not sure this is actually an INL error - it could still be some variation in the 5 V supply, that effects the charge injection. In normal operation the auto zero would take care of most of this.

Again with the smaller integrator resistors I also ran a noise test with a short over a longer time. Attached is a report from the Alavar software. The vertical scale / units are  µV.  The horizontal scale is at some 70ms for 2 conversions and sending the data separately.  So the short time noise (1 st point of Allan dev. curve) is at some 560 nV reaching the level of the 8 digit meters.
For longer times the noise is not going down, as this test is without auto-zero and thus has quite some 1/f noise from the OPA145 in the input buffer and OPA1641  (amplified 2 times) from the integrator.

[Kleinstein]

A small update on the ADC with a few crude INL tests:

The early test here showed quite some self heating effect. So directly using the current ADC would result in rather poor INL (expect some 10 ppm of INL error). To circumvent the self-heating effect I use a fast gain measurement. This is not a new Idea, but was already used in old DMMs like the Keithley 19x series. So the ADC measures a sequence of input signal, zero and 7 V reference (LM399). The result is than
U =  (U_signal - U_0) / (U_7 - U_0)
This improves the gain stability and INL, but adds a little to the noise, effectively adding the ADC noise to the reference. Because the ADC itself is very low nose this is not much compared to the LM399.

For INL-tests I use a simple LM399 based reference source with an amplifier to some 9,3 V, divider with 12 equal resistors and buffer. So there are 2 buffered outputs: one at 9.3 V and one selectable voltage from some 0.775 to 9.3 V. The reference is powered from a separate old style 12 V wall wart.
 
For choosing the signal voltages a simple mechanical SPDT switch for one side (ground of the ADC) and the MUX on the ADC board for the other side are used. A sequence consists of 4 voltage readings, that includes 1 or 2 zero readings. Ideally the sum of 2 readings minus the 2 other readings should be zero if the ADC is linear - a deviation indicates an INL error.

The first test is the classical turn over test, measuring the external reference in both polarities and 2 zero readings to compensate for possibly input dependent offsets. At 9,3 V and 7 V the turn over errors turns out to be small somewhere in the 1 µV range.

The next INL test is measuring 2 voltages that in the sum make up the fixed 9.3 V level.
Andreas describes such a test here:
https://www.eevblog.com/forum/metrology/dmm-linearity-comparison/msg1351979/#msg1351979
So far the tests show an error of some 5-15 µV for the sequence (tested at 4.65 V, 3.88 V and 3.1 V so far). This corresponds to an INL error of some 0.3 - 1 ppm. This is not as good as hoped for, but still good for a low cost ADC.

There still seem to be some EMI issues, as the exact position of the cables and shielding makes a difference. Offsets of the nominal zero readings (up to some 6 µV) seem to be more due to higher frequency effects effects than thermal EMF. Also the bootstrapping of the buffer is not yet working well and loading the inputs quite a bit on switching. Before more INL tests (more points and more repeats to get lower uncertainty) these 2 weak points should be addressed first.

[iMo]

Schematics..

[Kleinstein]

The reference unit is similar to the schematics shown: the feedback to the OP is one step further up the chain and thus only 9.3 V. My resistors are 1.91K (some NOS I had laying around with reasonable good matching, though only marked 100 ppm/K grade).

For stability check I also ran the usual reading of the external reference. The curve shows visible popcorn-noise and also a few outliers towards the low side.  I am not sure what causes the outliers  - they are even more obvious in the raw data, only effecting the external readings.
The noise is visibly higher for reading the external reference compared to the ADC internal one. So most of the noise is likely due to the 2 references (LM399 AH and LM399H). The jumps from the popcorn noise are at some 3.5 µV (better visible from averaged data) - I think this is about normal for LM399.

Due to the background zero drift it is a little hard to tell which of the 2 reference is causing the popcorn noise.

There is some filtering for the reference at the ADC, though currently not much (only 1.5 K and 1 µF). There may be a chance to use more filtering (e.g. some 5 K and some 10 µF).  Usually reference filtering is not considered that effective, but it may be worth it to have the same reference level for all 3 conversions that make up a reading.

[Andreas]

Hello,

You could put a 1-10nF capacitor across external input + GND of the DG408 (IC7) to see wether the voltage drops are EMI-related or not.

with best regards

Andreas

[Kleinstein]

I changed the buffer amplifier supply from true bootstrapping form the output to a system with an extra OP buffer (OPA172) to drive the supply voltage center from the input signal. This seem to have improved on the possible EMI issues. At least it does not seem to be that sensitive anymore. There is still some effect from switching, but it got significantly better (e.g. 1/4 the size) than with the old bootstrapped version.

One input was fitted with 1 nF (towards signal ground), but no difference visible. It's more like the cap could increase the effect of switching related charge pulse. Maybe I may have to add a kind of pre-charge phase, so that sensitive inputs don't see the full switching spike.

However at the currently rather high temperatures (some 27 C room temperature) the leakage current (likely from the DG408) is rather high: I measured some 250 pA (some 85 µV extra offset with a 330 K resistor) for one input. So the offset voltages could have been just input current and the 22 K resistors at the inputs. So far I have not cleaned the flux - so it could be some leakage from there too.

The next test would be using DG508B (with lower specified leakage) instead of DG408.

[Andreas]

I changed the buffer amplifier supply from true bootstrapping form the output to a system with an extra OP buffer (OPA172) to drive the supply voltage center from the input signal.

Interesting. Any schematics available?

One input was fitted with 1 nF (towards signal ground), but no difference visible.

Where exactly did you place the 1nF? before or after the 22K (across the input protection diode).

with best regards

Andreas

[Kleinstein]

The cap is directly at the DG408 mux, so behind the resistor. My external reference source is not made to drive a capacitive load (just the OP output)  so I could not have the cap directly at the input.

Attached is the schematics part of the new buffer. The green  (old type) LED is replacing a 2.7 V zener. The zener diode is 5.6 V.
I could build the modified circuit on the board, because there is a footprint for an optional OP (for a totally different option)- so I was lucky to have option with just a few short bodge wires and the LED at an angle.

[iMo]

Why do you connect pin 3 of the OPA172 to the input via 12k? I would wire the pin 3 directly to pin 6/2 of the OPA145..
Why 5V6 only?

There is some filtering for the reference at the ADC, though currently not much (only 1.5 K and 1 µF). There may be a chance to use more filtering (e.g. some 5 K and some 10 µF).  Usually reference filtering is not considered that effective, but it may be worth it to have the same reference level for all 3 conversions that make up a reading.

What would be max acceptable thermal noise of that resistor?

[Kleinstein]

The 12 K resistor is a little on the high side and one may not even need a resistor.  I added the OPA172 as a kind of after-though / bodge and I needed some distance for the resistor anyway. The exact resistor value should not matter as the OP172 is only good for a first approximation.

The OPA145 is only powered with some 5 V so that the total output range is large - some -14 V to about +11.5 V despite the limited supply (+-15 V). The purpose of the driven supply to the OP is to improve linearity. The OPA145 is quite good for a normal OP, but it is still not sure to get better than 1 ppm INL. The driven supply should ensure very good linearity for the buffer.

The resistor in the filtering adds noise (thermal noise and resistance in combination with the OP's current noise). The noise has to be compared to the reference noise. For the LM399 this is some 100 nV per square root of Herz. In addition there could be some drift from the OPs bias. I consider up to about 10 K practical. For the very low frequencies filtering is not really practical - I see the main gain in the range up to a RC value of some 100 ms. This is to average over a measurement cycle of some 20 ms zero, 20 ms the external signal and 20 ms of the reference. The reference value is only important for the signal conversion and thus only 1/3 the time. Also using the other 2 thirds of the time should help reducing the noise. Lower frequency filtering is less effective as there is the time for the conversions doing averaging anyway.  In stead of very low frequency filtering (e.g. 20 K and 500 µF (low leakage)) I would prefer a 2 nd LM399.

The other point would be filtering of the signal itself - this would be filtering before the MUX - again mainly to bridge the 60 ms measurement cycle. However this would effect the settling at the input. So one would still need the choice of the direct signal or the filtered signal.

[Rerouter]

Don't suppose you would have an image of the current PCB? Trying to understand a few of the things you are facing in hopes to improve this project.

I've redrawn the schematic as it makes sense to me, to unwrap a lot of the crossing connections, (If a component is in the 200 range, I added it, If its in the 300 range and not 381, then I was not able to read the existing reference, and IC3 became U1, because there was a conflict in names when renaming then to U instead of IC, and TC became Q for transistors)

Also while copying out the existing one, Caught some things that I don't quite follow?

1. R23 connects to normal ground, not the Analog ground, Is that intended, or ignored in your current layout?
2. Your +15V rail does not have a 100uF output capacitor like the other rails?

And finally, I can see a number of values have changed since your initial schematic based on the bootstrap supply, any chance of an updated schematic?

[Kleinstein]

The buffer amplifier has changed and seems to work much better now.  It may be possible to simplify it a little (e.g. only using a current source from the positive side and the OP directly to drive the negative supply of the OPA145). For the MUX I have tested both DG408 and DG508 with not much difference. The extra offset with an additional 330 K seem to be more due to a transient effect, and not just a simple bias current. So there still seem to be some smaller issues with the input buffer / mux.

For the rest of circuit there are no larger changes. R1,R2,R3 where changed to some 25 K (2x50 K in parallel), though the 46 K version was about as good (slightly higher noise, but possibly better linearity). With only 25 K the integration cap also got larger (now 2.2 nF (PS)+1 nF (NP0) in parallel).

The board now actually has the LM399 reference as in the plan (before only a LM329 was populated).

C24 (100 µF at the LV4053) is no longer used - it did not help.

R23 goes to the normal ground. This is intentional not to send modulated current to the analog / signal ground. The exact level is not critical anyway as the main purpose of this resistor is to keep the voltage across D2 small and send the current from D10 to ground. Ideally the voltage over D2 should still be small in the critical final phase, like less than 100-200 mV. The normal GND and AGND are connected with a wire bridge (red bodge wire on the bottom) anyway. So the difference is small, more like possible spikes and maybe a few µVs.

The redrawn schematics looks good in most places, but has a few quirks:
Pin3 of U2 going to the point between R10 and R11.
R13 should be larger - I think some 47 K.
The reference signal to U9 pin3 is coming from the capacitor C13.  C13 will likely soon change to 4.7 µF for more filtering of the reference.

For the inputs, I have only one of the input with an extra filter cap - the cap is not working really well, as it take quite some time to charge. So the 1 nF cap(s) at the DG408 will likely be reduced - more like 100 pF.

The picture from the bottom side is not very sharp, but it is very difficult to read the OP labels anyway.

[Rerouter]

Found an error around U13 on my old schematic, and implemented the changes you mentioned.

Simulating the integrator section seems to show a null point around -9.78mV, was that intentional? (the integrator voltage when the comparator toggles)

When the integrator gets above about +0.5V U13, mcp6002 is outside of its common mode range (vss - 0.3), It does not exceed the maximum spec, just leaves the common mode, and left wondering if that unused amp in U13 could be used as a workaround

When your down to nV from null on the integrator, does U13 actually perform usable amplification, e.g. does adjusting the 10K trimpot effect anything, as if so you could change the trimpot to AIN0 and use an ADC pin to directly measure this pin if that would help any part of the calibration, and leave it connected via the ADC mux for normal operation. (right now it seems its output would represent about 0.8uV on the integration capacitor at the null point)

[Kleinstein]

A small offset at the integrators output, when the comparator switches is not a problem, as only differences matter. The exact trigger point is set by the 10 K trimmer.  U13 sometimes goes into output saturation, but should not go out of common mode (as the + input is always at some +150mV). The inverting input voltage could reach slightly negative voltages, but this is only during phases when it does not matter.  So there is no need to work around this, just slightly different resistors could probably avoid it. The DC level is more adjusted to stay in the linear range of the slope amplifier (NE5534 with the diode feedback).

The 10 K pot does change things: it sets the trigger point for the comparator and thus the typical offset the ADC in the µC sees and which part of the slope amplifier is used. However the setting only needs to be inside a rather large valid range, the exact setting does not matter. So using a multi-turn trimmer is over-kill. Currently I have something like 1 turn of the pot that only changes the part of the ADC range used, but not the final result.  The right setting of the pot can change a little with software changes or a different capacitor so for development the pot is good. A final solution might get away with fixed resistors or maybe 1 or 2 bits of R2R DAC. There is no real need to trim the pot for calibration -  mainly avoid the limits of the µC internal ADC.  With more gain to use more of the µC internal ADC resolution the setting would get more critical. This could be the case in a version without the slow slope (e.g. symmetric reference).  This could be an option as it would allow to use a standard resistor array for the reference amplification.

The 2nd half of the MCP6002 is currently used to measure the average integrator output voltage  (3 bodged in resistors and the yellow cap on the bottom). An alternative use (planed on the PCB) is to use it to read the temperature - though at a position that is not that good.

LSP6 is a test-point to check the integrator settling (C17, C37, R10, R20), the resistor is there to reduce a possible probe effect.

C17 is  not at 2.2 nF but 220 pF , and C37 is currently not populated.
There is another mistake in the redrawn schematics: R24 is between U4 and U13B, not in series to R40.

To an earlier question: The actually is a 100 µF or similar cap at the positive supply - it's bodged in, near U6.
Originally I only had the capacitor at the negative supply, as some 7915 do like capacitance with ESR, the 7815 don't need it.

Another bodged in change is a ferrite bead in the VCC supply to the µC. This also feeds the DG408 5 V supply.
The current board uses a boxed oscillator, but just a crystal at the µC should work too and was tested before (the boxed oscillator did no give a significant improvement).

[iMo]

The input buffer - while simulating it the output voltage is not positioned in the middle of the OPA145 Vcc/Vee, something I would expect..

PS: maybe a "typo" in your above schematic??

[Rerouter]

IMO, that is because he us using a LED and a zener, there combined voltage drop is what sets the supply voltage for the op amp, but as each contribute a different amount of voltage while being biased at the same center point results in the output being more towards the LED biased rail.

[iMo]

I would plead for a symmetrical version, for example this one creates 3.9V at ADA4528 (for example).
PS: the current via the LEDs is aprox 175uA..

[Rerouter]

while you have that loaded in your simulator, could you see if there is any better linearity or voltage headroom gains from altering any of the 7 main resistors (parametric analysis)

[iMo]

The sim files..

[Kleinstein]

The slightly asymmetric supply to the OPA145 is intentional: The OP145 is single supply ann can work well with low voltages, but not well near the positive supply. In the current circuit only the 5.6 V zener - VBE set the supply. The LED sets the common mode voltage seen by the OPA145 - the point in the center is not that special. At the lower limit the OPA145 can this way go lower (and turn the LED off) and still have a 5 V supply and give a good output. In the circuit with 2 LEDs the working range is a little smaller, as the supply voltage would drop low.   

The other point  for this choice was just parts available: I have plenty 5.6 V zeners (hoping for a lucky low noise type), but not many low voltage zeners, suitable LEDs to get a sum of some 6 V. I may test a slightly high voltage zener, just in case I run to close to the positive limit or low in supply.

For the reference popcorn noise I did another test, measuring a 9 V battery. As expected there is popcorn noise too - so chances are both references contributed to the popcorn noise. At least the LM399 at the ADC is no exceptionally good.

Another test is more confusing: The ADC is programmed to make 4 conversions  for 4  MUX channels in a cycle. Two channels are reading zero, one with a 22 K resistor and one without (the internal zero) . The 3 rd conversion is the internal 7 V reference. The 4 th conversion in the cycle is varied to different voltages.

Ideally the 2 zero reading should give the same result, maybe a tiny offset from bias current times 22 K. However the difference does depend on the 4 th channel, which is also the reading before the 2 zero readings. So there seem to be some kind of memory / spill over from one reading to the following conversion(s). The test was done with with 1 PLC and 2 PLC conversions and than averaging over some 100 cycles to reduce noise. A seen in the graph the difference is about proportional to the 4th reading voltage, at some  1 and 0.5  µV/V. So the effect is larger for the faster 1 PLC conversions, which is not such a surprise.

The change in MUX setting is at the beginning of the rundown phase. So there are some 200 µs (relatively long because of the aux reading) for the input buffer to settle before the next conversion starts. Usually there are no specs for settling to the ppm level, but I don't expect the buffer to be that slow.

[iMo]

With your buffer schematics (opa140+opa171, post #33) the settling from 7V to less than ~1uV takes aprox 360us with 1nF and 37us with 100pF C16 cap.

[Rerouter]

There is some drain capacitance on each switch, I would imagine this is what is causing the transition your seeing. so there is essentially 40-80pF per switch if I am reading this correctly.

[splin]

How come for your linearity tests that you used a seperate reference to feed the divider generating the test voltages rather than using the ADC's reference? Instead of adding the noise from the two references it should eliminate most, if not all, the reference noise when measuring the test voltage? Obviously the ADC's transistion noise would still exist during the signal and zero measurements.

[Kleinstein]

I have done 3 types of linearity tests so far. The first was using 2 modes with different run-up to measure the same voltage - here only the very short time variations of the reference enter here and these are not that large and could be filtered. This test is mainly for the fine wiggles, a little more than DNL and no including some effects
The 2nd test  The linearity test is as suggested by Andreas. This test needs an isolated reference (e.g. some 10 V)  and 'divider', so that one measures 2 voltage that in the sum make up the '10 V'. Having the reference isolated is essential here, as the ground connection is moved.
The 3 rd test is the classical turn over test. So measure a voltage positive an negative, by reversing the leads. This also needs an isolated reference.

I had planed another test test in the ohms mode - however I reused the part planed for the current source for the 2nd OP at the buffer. So I will probably not do this test with the current board.


For the odd carry over/slow settling problem, I did a few more test: Changing from DG408 to DG508 makes little difference. Also removing the 12 K at the OPA172 input has no effect. However additional capacitance (or just a cable) at the mux output makes things worse.

The capacitance of some 60 pF due to the MUX itself should not produce a significant delay with the 22 K series resistors. That's only some 1.2 µs time constant and thus much shorter than the 200 µs delay (rundown with auxiliary reading). If it is just a simple exponential decay it would take an RC of at least some 20 µs and no more than about 5 ms (as the slower conversions are less effected).