DIY high resolution multi-slope converter

[dietert1]

Thanks for the link to the noise measurement results of antintedo. I thought there were some new results to confirm them.

The LT5400 datasheet specs -10 ppm/K < TC < 15 ppm/K for the absolute resistor value and there is no spec on how stable the absolute TC will be. Yes, any mixing with other parts will ruin the tracking specs except for fine tuning the residual imbalance of 0.01 % to 0.025 %.

Regards, Dieter

[Kleinstein]

The plan has extra optional resistors in parallel to the array - these are alternative footprints for my board, e.g. for THT types like PTF56 or for a first test and to check other resistor values. It won't make sense to have them together with the array.

When using a LM399 reference, the NOMCA resistors are good enough. The variations in ADC gain are visible (e.g. 0,2 ppm popcorn like jumps), but less than the reference noise. So there is a limited advantage of using a LT5400 with a LM399 reference. One could still consider 2xNOMCA with 10 K, so 4x10K for each resistor. This would be for slightly lower noise and less self heating

On the other side, with a LTZ1000 reference, it would be bad to have the cheap resistors that add something like 2 times the reference noise. In this case using 1x10 K and 2x100K LT5400 would be more appropriate.  Even with only 1 x 100 K the additive noise would likely be not that bad and not much multiplicative noise from the resistors.
Even with the LT5400 one could still use a parallel resistor to produce the asymmetry, as the parallel resistor is larger something like 10-20 times. It is not perfect but could be acceptable with an external 5-10 ppm/K resistor. The extra center shift can be better if < 5-10 ppm/K matching is used there.

@ Rerouter: thanks for noting the missing (lost) supply at IC4.

There is no LT5400 with 20 K !  2 x 20 K in series is the preferred option for a single NOMCA network.

So with LT5400 one would have 2 x 10 K in series and thus 20 K total. This is on the low noise but likely higher INL side. It may also need a slightly larger integration cap.  For the test 20 K (2x10 K PTF56) worked, but there is a chance to get better INL with higher resistance. So it is an option if lowest noise is the target, but one has to expect a little more INL.
The ADTV6581 uses an even slightly higher current level (20 K with 15 V reference level), so it is not absolutely out of range.

For better INL 2x100 K in parallel is likely better, though slightly higher noise. In addition 1 x 100 K is also an option (slightly higher noise).

[iMo]

I think you have to distinguish between the 399 and LTZ versions of your ADC.
With v399 I would expect the 34401-like performance. Two LT5400 packages (say $15 each) would be ok for such a version (LT5400-10k for the Vref and LT5400-100k for the integrator).
With vLTZ Vref the costs will be v399+$200 anyhow, thus 2 LT5400 packages for the integrator resistors (100k||100k) will not add that much.

[Kleinstein]

Yes one has to think about 2 versions:
 
1) A lower cost version with LM399 reference. This could use 2 x NOMCA (10 K + 20 K).  The noise level for the reference is like the 34401 (maybe a little more), but the ADC noise (e.g. relevant for small fractions of the full scale and fast (e.g 1 PLC) readings) can be much lower, more like the 34465. It would be more like 3 x NOMCA 10 K and 2xLM399 to get a slightly better version. The resistors at the ADC are a little more important than the ones to scale the reference. Using LT5400 is possible but not really needed. Besides the higher price the LT5400 are also more difficult to solder, especially if not using solder paste and hot air. The other reason for the LT5400 would be the better TC matching to reduce the thermal INL.

2) A Version with LTZ1000. This would essentially need LT5400. With the cost of the reference using 3 x LT5400 would not be a big factor. There is no need for the higher grade, the simple grade (more like $10 each) is sufficient, as the On resistance matching in the LV4053 would not be much better than 1%.

[Rerouter]

For the 2x lm399 method. Are they directly wired in parellel or is that anything else being used to sum them.

Have the reference and most of the adc laid out to the new schematic. Just working out how to make the input buffer nice.

i can make it so there are 3 series sets for the input if 30K really is the sweet spot. Should not effect things too much.

[Kleinstein]

For 2 x LM399 one would use 2 separate resistors to the filtering and separate resistors to provide the current. The heaters would be directly in parallel.

For the integrator resistance I don't know exactly where the sweep spot is. More resistance adds a little to the noise (like twice the resistance at the input)  and too low can increase the INL. I have tested 20 K to 105 K so far with no big problem. The last INL data are with 20 K.  With 10 K resistors it did not work so well (too much drift), but this could be from the resistors used (power type wire wound). Maybe I have to repeat the test with different resistors, to see if there is significant more INL.

30 K would not be that much different from 20 K anyway.

[Rerouter]

Would you be able to describe what function IC20/U20 would accomplish, seems like your adding currents to the slope amplifier, but not clear what it does.

Edit: also the current mirror with T5 / T6 and why it connects to the integrator output?

[chickenHeadKnob]

For 2 x LM399 one would use 2 separate resistors to the filtering and separate resistors to provide the current. The heaters would be directly in parallel.

For the integrator resistance I don't know exactly where the sweep spot is. More resistance adds a little to the noise (like twice the resistance at the input)  and too low can increase the INL. I have tested 20 K to 105 K so far with no big problem. The last INL data are with 20 K.  With 10 K resistors it did not work so well (too much drift), but this could be from the resistors used (power type wire wound). Maybe I have to repeat the test with different resistors, to see if there is significant more INL.

30 K would not be that much different from 20 K anyway.

What physical mechanism(s) would you attribute to causing INL ? Is it simply self heating of the resistor or other factors?
Thank you for all of your efforts.

[Kleinstein]

There are several mechanisms that can contribute to the INL, some of them are likely negligible. The main INL sources I know are:

1) heating of the resistor at the integrator input. This gives a contribution proportional to the resistor TC (or TC match if tight coupled) and U³. With resistor arrays there can be also a U² part, but the AZ mode will suppress most of this.

2) DA in the capacitor hides part of the charge and gives it back in the next conversion.  The slow part of the DA follows the average integrator voltage.

3) Switching the reference before the integrator input is fully settled gives a small error due to the input voltage of the integrator. Luckily with the simple 1 test per period mode for the run-up, the number of short reference pulses is proportional to the input voltage. So the error would be a linear step function, so that only the error from single steps would be real INL. The rest would be just a slight change in gain.

4) Having two short phases close together could have some additional effect, e.g. with the 4053 supply not settled or a tiny rest at the integrator. This case happens more often near zero and less frequent at the extremes. This effect is expected to give some u² or similar dependence, if visible at all. Longer time for the short phase should reduce this effect.

5) The settling of the integrator can depend on the current the OP drives. The OPs GBW or phase reserve seems to depend on the output current.  As the settling part can contribute to a small offset to the integrator input, this effect can contribute to INL. The effect on the settling is visible on the scope and the extra current mirror can to a large part suppress it - however with no visible effect on the INL. So this mechanism still seemed to be rather linear. A similar effect comes in combination with short pulses, as the effect of a short pulse may depend on the current.

6) leakage on the board, at the resistor array or 4053 can couple the input voltage a little to one of the references. This would give a U² contribution, as the time that reference is used depends linear on the input.

7) there can be some coupling from the input buffer / input to the integrator to the reference circuit. This can be thermal or through the ground or maybe the supply.

8 ) The buffer may still be not perfect, even with using a bootstrapped supply. Load the output was one such effect, that was visible before adding a bias.

9) some couplings, e.g. from the comparator / slope amplifier to the clock. This was a problem before using the canned oscillator.
  Together with the extra sync FF this effect should be minimal.

10) if only a 1 OP integrator is used, the residual voltage at the input in combination with mismatch of the resistors can cause an error.
   The 2nd OP in the integrator should suppress this part to a large part. With the resistor arrays the mismatch is relatively small and a 1 OP integrator may be possible.

11) thermal coupling in the 4053. Due to the low resistance the power is small, but there still is some heat.

12) During the transients there can be a small current at the OP inputs at the integrator. Though JFET OPs the ones used have protection diodes that can start conducting over some100 mV. This is better than with BJT based OP that can start to have more current beyond some 40 mV, when the input stage starts to become nonlinear.

13) The fast part of the DA depends on the very end of the run-up and the charge measured. This can give an more local INL error especially at the steps when the run-up part changes. The fast DA is also visible as some drift of the residual charge, but the effect is usually small with a good cap and some waiting time in the run-down. 

Then there are also those effects I still missed and a few more I know, but with very small effect.
Quite a few of the possible INL source are switching related, so that very fast modulation to reduce the DA error is not only positive.

The idea of IC20 (DG419 at the slope amplifier) is to modify the feedback during run-up. During run-up extra signal from the average integrator output is added. This would reduce the average integrator voltage and this way the slow part of the DA, one of the know larger INL sources. This way lower modulation frequencies are possible, with less switching related errors.  As an additional side effect there is less loading of the integrator during run-up and the small resistor for low noise is only chosen for the run-down phase, when it is needed. I have not tested this, so just an idea that has a good chance to work. If not, one can still keep the DG419 not populated and change the one resistor at the slope amplifier input.

The current mirror to the integrator output is to keep the output current of the integrator about constant, as it was observed that the current has a visible effect on the OP speed/settling. The current is not constant all the time - there are still the jumps up and down by the reference, but the two level for going up or going down would stay about the same. The additional offset shifts the current to the one side that works better for the OPA172.  The improvement of the settling is visible on the scope (see the scope traces a few posts back) - but not much INL effect, even with 20 K at the integrator.  . So the current mirror is optional for a possibly small effect, not yet detectable. Especially with higher resistors at the integrator one could likely skip the current mirror.

[Rerouter]

For me it looks like the main points are
- prevent phase reversal in the op amps. Not hard just some math.
- reduce leakage paths to critical nets. Already partially done with the guard traces where applicable
- reducing the slope amplifier / analog comparitors radiated EMI. Done for the slope amp. Will look into for the comparitor.
- protect the clock from external noise sources
- run some thermal FEM solvers to try and keep heating uniform around critical parts of the board. Currently poking the kicad community about this and there are starting to be better guides
- keep the option for the input array heater to reduce the change in temp as much as possible.

[Kleinstein]

Most of the OPs used don't have a problem with phase reversal. The input common mode range is still a thing to watch for because of the differenc supplies.

For the clock, using a canned oscillator and the 2 flip-flops to synchronize the 2 critical signal the timing is critical only for this rather small part.

EMI is one of the more tricky parts. There are fast switching events and a mixed digital / analog circuit. EMI not only effects the analog world, but also the digital side. Without the FF for sync the ADC in the µC did have some effect on the timing of the outputs - only very small and visible with a poorly chosen modulation frequency. So EMI is not only digital effecting analog, but can be other way around. I don't think radiated EMI is a main problem, the first point is coupling via the supply and ground. For this reason there are resistors in the supply at quite a few point - both possible sources of trouble and sensitive parts. So interference would go through 2 such filters.
There is still an odd, likely EMI related effect: the output state of otherwise unused IO ports at the µC effects the result: even with the input MUX (DG408) removed from the socket the MUX setting from the µC has some effect (~ 1 µV) - more than I would expect from capacitive coupling.


Thermal coupling should not be so critical that it needs FEM. A static thermal gradient would not be a problem. If at all it is about heat sources that change with the input signal.

[Rerouter]

EMI is not as evil or hard. Just takes a lot of thinking. Its partly why my earlier boards had such a weird ground layout. I was going through what ground current each device put out. And tried to shift anything that I could off from the 'signal ground" that changed too much or was a significant current. What your seeing with the micro is likely a combination of the ground voltage changing with supply loads combined with the micro control signals being very fast (also why i have the resistors on all outputs in my diagram

I will keep walking through them for now. After all no one said it would be easy

Sorry not phase reversal. Meant crossover distortion to avoid the non linear transisition between sinking and sourcing current.

Edit: the FEM solver also gives me ways to analyse how currents effect voltages on other nodes. Trying to get the PSRR in our favour

[Kleinstein]

The odd effect of the IO pins controlling the MUX is not effected by series resistors at the pins and there is no current flow as the pins are open or going to the CMOS inputs of the MUX. I think it is more like adding capacitance to the ground side or VCC side. That would be the main difference. The other point is the change in level that may cause capacitive effects, but it does not change with an added cable. So still confusing. Even if odd the effect is like an offset to each MUX channel and thus possible to correct.

Cross over distortion at the OPs output is in deed a possible factor, that I learned here can be important.  One could add more bias (lower value for R76) to the current mirror to avoid the cross over also for the integrator. Currently the normal case is to have the current to change sign.

I know the problem with ground currents. This is the reason for the +-15 V supply isle for the integrator an slope amplifier with C6 going directly to the signal ground. This is to compensate the changing reference currents from the 4053. R31/R32 in the supplies are large with 150 Ohms to avoid the AC current to go a different way. The alternative (no more C6) ground buffer is also intentionally from that supply isle. Except from C6 and the 4053 the other things connected to the signal ground are more like low current or constant current like the reference.

[Rerouter]

Would you be able to upload your schematic in eagle xml format? would like match up the references a bit better between our 2.

[nnills]

I am new to this project and would like to understand how it works. I was not able to find: the kicad files, the software and a theory op operation. I suspect the letter one does not exist but where could I find the other two?(on github?)

[Rerouter]

Modified rev-2 is the current kicad files I am working with, had to pull things back apart while I updated the chunks to the current schematic

Theory of operation is a multislope converter, with the input left connected you switch between the 2 references in a pattern depending on what the output of the comparator measuring the output of the integrator was (There is a psudo-log amplifier between these 2 to amplify the difference) with the goal to keep it as close to 0V as possible, you take note of how many counts it was high, and how many it was low, and by knowing the reference voltages can find the slope that matches only that voltage. and use an ADC to capture the residue left afterwards to gain some extra resolution out of the result. (or so I think, going from memory)

Software Klein has released before, as atmega assembly from memory again.

There is a thread where a lot of this was discussed over in projects and technical, but can't find it right now.

[Kleinstein]

The theory of the operation is explained in the first few posts. There is also a version of the software, though an older one. So I add the current version of the µC SW as an attachment. The actual software has not changed that much, but some of the registers / constants got renamed - hopefully it is now a little easier to understand.  The circuit is there as an eagle file (zipped) and .png a few posts back.

For the theory of operation, the idea is to have a relatively simple multi-slope ADC with the µC to do the control. In short the HW is similar to the HP34401, while the control is more like the classical multi-slope with a run-down with a single slow slope. Most of the resolution is from the classical form and the µC internal ADC is used to replace the integrator reset and to add a little extra resolution. So instead of the reset the integrator charge is measured with the µC internal at the start and end.

The general idea with the multi-slope ADC is to integrate the input signal and apply feedback from the reference current during run-up. This phase takes up most of the time - in my case usually 20 ms. The keep the number of switching events constant there is a fixed frequency for the modulation and a fixed sequence the references are switched - only the time of few transitions changes. The feedback is the very simple form: a short (e.g. 1 µs) fixed positive and negative phase and than one longer (e.g. 8 µs) phase that depends on a single comparator reading. This gives some 2000 net positive of negative steps of 8 µs for the run-up part. The rundown part than disconnects the input and uses a variable length for a positive and negative reference to get close to zero.  The software has a timing resolution of clock 4 cycles and thus some 250 ns/333 ns depending on the clock( 16 or 12 MHz). To get the accurate timing the SW in written in assembler.

The way the slow slope is realized is a little unusual: the positive reference is a little stronger than the negative one and the two sources together give the slow slope of something like 1/20 the single slopes. The slow slope phase reduces the residual charge even further. The µC internal ADC than reads the small rest. Overall the run-down takes some 150-200µs, including some waiting time.
The contributions from the run-up and the fast run-down are linked by the known lenght of the run-up steps. So there are 3 contributions to the final result: one from the difference of the reference currents, one from the sum (= the slow slope) and the µC internal ADC. The relative size of the 3 parts is measured before in a separate calibration run. The ratio is stable enough that this only needs to be done once a day, week or so. The use of measured ratios avoids the need for accurate resistor ratios. The extra multiplications for the result are no longer a big deal for a µC. Currently the ADC part sends out raw results via the UART and the combination of the 3 parts is done at the PC.  The normal mode of operation is to alternate between the actual input signal and a zero level. So a full reading takes some 40.4 ms.

[Rerouter]

The eagle file was the binary format as best I can tell. The xml one i can import into kicad.

[iMo]

I am new to this project and would like to understand how it works. I was not able to find: the kicad files, the software and a theory op operation. I suspect the letter one does not exist but where could I find the other two?(on github?)

https://www.eevblog.com/forum/projects/multislope-design/msg1376978/#msg1376978

[Kleinstein]

I am new to this project and would like to understand how it works. I was not able to find: the kicad files, the software and a theory op operation. I suspect the letter one does not exist but where could I find the other two?(on github?)

https://www.eevblog.com/forum/projects/multislope-design/msg1376978/#msg1376978

That other older thread was from another user starting to design a MS ADC. It was kind the starting point for the ADC shown here, but it also contains a lot about other versions and older ideas, especially at the beginning. Near the end much is about the ADC used in this thread.

The eagle file is the binary version - the only one available with the old eagle version (5.12) I have.

[branadic]

About the choice of opamps in such a design, there is an interesting read about opamps usable for ppm range today:

https://www.analog-praxis.de/lassen-sich-mit-operationsverstaerkern-wirklich-genauigkeiten-im-ppm-bereich-erzielen-a-912607/

-branadic-

[MegaVolt]

Full text:

[MiDi]

The eagle file was the binary format as best I can tell. The xml one i can import into kicad.

Maybe the only thing I can contribute 

[Rerouter]

Thank you very much for that,

R48 is a floating connection
IC13's (pin 7) output is floating
on your schematic klein.

Going through and matching up references that where too hard to tell before.

[Kleinstein]

Thank you very much for that,

R48 is a floating connection
IC13's (pin 7) output is floating
on your schematic klein.

Those two points were misplaced dots from moved parts. In my program versions they are still connected.