DIY high resolution multi-slope converter

[saturnin]

I was interested only in DCV signal path, so I didn't go through all blocks. As for DCV ranges, I can see two mistakes (due to no hints in the documentation): lower leg of Q203 is connected to U253 output and Q201 input is connected to U255 output.

[Kleinstein]

If Q201 goes to the input or output of U255 probably does not make a big difference.
Knowing that the lower leg of Q203 goes to the output of U253 (= ADGND) is good.

Another part that is not that sure / clear and a little odd is the part with R313, R314 going via U242 to the input of U253.  To me that part does not make much sense. The current sources for the references in the ADC circuit are a kind of elegant way to allow for a (small) difference between the input ground (ADGND) and the reference low side. However the ADC circuit still needs ADGND to be close (e.g. < +-1 V)  to ground, so the signal at U253 can not be much different from ground.

The main part still left over is U236 (= OP27). It may be part of the buffer with U217+U257.
There is also no more free input at the MUX U222. So I see no way that there could be a kind pseudo-differential mode hidden.

U256 also does not appear in the descriptions - these 2 OPs are likely used with the input protection (e.g. bootstrapping the protection) and maybe part of the input buffer (e.g. part of the floating supply or current source).

[saturnin]

Another part that is not that sure / clear and a little odd is the part with R313, R314 going via U242 to the input of U253.  To me that part does not make much sense. The current sources for the references in the ADC circuit are a kind of elegant way to allow for a (small) difference between the input ground (ADGND) and the reference low side. However the ADC circuit still needs ADGND to be close (e.g. < +-1 V)  to ground, so the signal at U253 can not be much different from ground.

The ADC needs to measure signals from different sources: e.g. voltage reference, input signal etc. Based on a given signal the proper ground is selected by U242. In reality, voltage reference and input signal grounds are the same wire, but they need to be measured as close as possible to the signal location to avoid errors caused by voltage drops along the wire. I would guess there are max. tens of mV difference between REFLO and COM grounds.

The main part still left over is U236 (= OP27). It may be part of the buffer with U217+U257.

In KEI2001 +5V ground and +/-15V grounds are shorted directly. Not so in KEI2002: +/-15V are referenced to COM while +5V is referenced to "Common 3". Still you need to define relationship between COM and "Common 3". U236 is used for this purpose. It is a unity-gain buffer. Its input is connected to ADGND and output to "Common 3". It probably helps to isolate COM and "Common 3" yet it keeps them at the same potential. Quite surprising for me.

U256 also does not appear in the descriptions - these 2 OPs are likely used with the input protection (e.g. bootstrapping the protection) and maybe part of the input buffer (e.g. part of the floating supply or current source).

U256 powers input stage of the input buffer.

[Kleinstein]

For the 4 wire Ohms mode Ohms sense low is connected to the ground side buffer (U253). So in theory there could be more than 10 mV, though in many cases it would be less. The other grounds are connected and the difference would be even less (no extra connector to an external reference), so it would be only trace resistance.
Thanks for explaining the function of U236. Having the 5 V ground relative to the output of U253 and thus ADGND makes sense, as the ADC contains a few critical HCxx chips. The switch resistance and speed would be effected by the 5 V supply and digital GND level.

[ogden]

Just stumbled on "precision" mux http://www.ti.com/product/TMUX6104 with special charge-injection cancellation circuitry (-0.41 pC in the full signal range). TI article about charge injection. For those who already know - sorry. Others may find something new, perhaps.

[coppice]

Syncing an MCU's ADC with such external events is difficult.

With some MCUs its difficult, but with some its trivial.

[iMo]

Here is a config for the integrator switches:
http://www.ti.com/lit/ds/symlink/tmux1134.pdf

[Kleinstein]

Just stumbled on "precision" mux http://www.ti.com/product/TMUX6104 with special charge-injection cancellation circuitry (-0.41 pC in the full signal range). TI article about charge injection. For those who already know - sorry. Others may find something new, perhaps.

The 4:1 mux is not that relevant for the ADC circuit. A corresponding MUX with 8 inputs could be an option for the input MUX. I still see quite some charge pulse with the DG408 or DG508, but I am not sure if this is from the MUX or buffer amplifier.
The ADC itself uses 2:1 switches at a fixed low voltage, where the charge injection is naturally low, even with not so special switches.


After quite some test, I finally found the weak point of the 2nd board: The crystal driven from the µC was somehow effected by the integrator signal. Changing the crystal to a boxed oscillator (this time 12 MHz) did the trick, even without the extra flip-flop.
For tests the integrator uses 20 K resistors (PTF56 type). In part this is to see if it may be possible to use 2x10 K from LT5400 in series and see in general if INL effects from high current get visible.  The current is a little on the high side and there may be some INL from thermal reasons or OP loading. So far no obvious extra error is visible. However the tests so far are not sensitive to ~ U³ type errors (e.g. expected from thermal effects). So it would need one more test that is also sensitive to U³ parts.

The attached files shows the difference between two speeds for modulation for negative voltages. One for the bad case with crystal and one with the canned oscillator-
The absolute value of the difference is arbitrary (additional charge pumping due to different frequency) and the slight linear slope for the good case is at least in part due to the continuous changing (capacitor discharge) voltage during the test. For comparison the second picture shows the comparable curve with the quartz crystal for the clock. The V shape error corresponds to the large turn over error seen with only the crystal.

[Rerouter]

A 20x improvement from 1 change, Now that is something very nice to see,

For the canned oscillator graph, how does that look if scaled by PPM of input instead of delta voltage?

[ogden]

Would be nice to see summary of current state of your project - including short description of the goal(s), pointer to theory of operation. Also some answers to main questions people who possibly just arrived here in this thread, would have. Like: It is open source (HW/SW) or not, where are design files/SW if any? What are "guaranteed by current design" specs expressed in common ADC/DMM performance figures?

[Kleinstein]

A 20x improvement from 1 change, Now that is something very nice to see,

For the canned oscillator graph, how does that look if scaled by PPM of input instead of delta voltage?

The improvement was relative to a bad starting point. So the unusual point was that the the crystal at the µC was unusually sensitive to external effects. The 2nd board is now about to the same level (maybe a little better) I have with the 1 st.  I also started with just a crystal on the first board, but there was a relatively small effect changing to the canned oscillator - because of this (and because it took some time to find one) I was so slow in changing to the canned oscillator.

The ADC full scale is at some +-10 V. So the variations of some 2-3 µV in the difference test correspond to some 0.2 -0.3 ppm of the full scale. However this test is not a full INL test: It does not include all INL contributions - mainly DA and switching effects, but not things like self heating of the input resistor and the input buffer.  On the other side it is also effected by variations in the 5 V supply effecting the charge injection and a non ideal test signal (e.g. nonlinear capacitance).

Compared to normal ADC / DMMs specs the current state is about the following:
Input range about  +11 V to -12.5 V, with some limitations beyond some +-10 V
Sampling rate: 24.5 SPS:  20 ms input, ~250 µs rundown , 20 ms zero (or negative input), ~250 µs rundown
Nominal (numerical) resolution:  ~28 bits
Noise: about 900 nV_RMS for the 24 SPS auto zero readings, difference of the 2 readings with 50 K input resistors.
For a DMM this would be called just 7 digit resolution for 1 PLC (24.5 readings/second)
With averaging one would be at 8 digit level for about 100 PLC.
However the LM399 reference adds extra noise with higher measured voltages. So the real resolution is more like 6-7 digits, limited by the reference. The lower noise is still useful at the low end of the range and for internal tests (e.g. ACAL).
Speed wise it is currently 1 PLC and for tests also 2 / 4 / 8 / 16 PLC, but more noise than averaging.
The Hardware should also work reasonable up to some 1000 reading per second with good resolution - currently the data transfer takes longer.
I have not tested the stability / temperature drift very much. The crude test gives some 1 ppm/K for the ADC gain in addition to the LM399 reference (should be < 1-2 ppm/K).
It somewhat depends on the resistor quality, so the spec limit would be more like 10 ppm/K, but the specs on the NOMCA resistors seem to be conservative and TC matching to the 1 ppm/K level seems more like typical.

The difficult part is linearity. Here the measurements are limited:
The turn over error (testes at some 9.3 V and 8.4 V) for both board is at some 3-8 µV, so around 0.5 ppm for each reading.
The wiggly part of the INL (mainly switches and DA) looks like better than some 0.3 ppm.
The thermal effect of the input resistor (U³ part) is expected to be less than 1 ppm FS for the TC seen in the gain drift.

Guaranteed by design is difficult as at that level.  The tricky parts are the small effect one does not fully understand or has no good control over (e.g. parasitic coupling, acoustic effects, RF interference, thermal effects, board leakage). So there is no guaranteed by design limit - it is more a best case scenario in the design, from the noise sources and INL effects one understands. This best case scenario is at around 500 nV noise (mainly the 50 K resistors) and ~0.05 ppm INL from  the DA (depends on the run-up) and ~ 0.2 ppm INL from the thermal effects of the resistors.

[Kleinstein]

A short update for today:
I did a few more turn over tests. This time for the run-up with the classic 3 phase  mode. For comparison 3 different lengths (667 ns, 1000 ns and 1500 ns) of the fixed phases were tested. The overall length for the cycle is 8.5 µs, so relatively fast, but not as extreme as in the 34401 or 3458 with some 3.2 µs cycle.

I found a relative easy way to make the test:  have the ADC sample 2 external inputs and calculate the difference. Those inputs are connected to the + and - of the external source. The ground connection is switched between the two sides with a mechanical switch.  This way the program continuously reads the same voltage. So even small difference get relatively well visible without much math.

The picture shows the turn over error for different test voltages and the 3 run-up versions.
For the mode with long fixed phase the 9.3 V point is already outside the range, and for the lower voltages there was hardly a turn over error visible ( < 1 µV range).  So while the two modes with the short times are not that good, the mode with a longer waiting time looks very good.
The turn over error looks about proportional to the voltage. That is a slightly different gain for the positive and negative side. This is what is expected for the error from short pulses. 

[Kleinstein]

A short update:
For a new board there is the choice of the resistors between NOMCA (e.g. 2x20K in series) and LT5400 (100K or 2x10K or 3x10 K in series). To check if using only 20 K resistance and thus more current at the integrator causes problems, I did a test with 20 K (the measurements before) and also 10 K resistors. I don't plan to use 10 K for the final version, this is more like a test to provoke errors than would come up with smaller resistance. So if 10 K works Ok, 20 k should be fine.

With more current the settling effects of the integrator gets more visible. The two attached scope pictures are for the integrator input for switching the reference from positive to negative and back to positive again. The scale is about 50 mV/div , 500 ns/Div (but no divs visible ) the time between the switching is 1 µs and the peaks go up to about some 150 mV (same scale for both pictures). The two pictures are for 0 and some +6 V input voltage. One can see that the settling after the switching is faster and better with positive voltage. This also explains, why the step from negative to positive ref looks so much better.
This shown that the OP (OPA172) in the integrator behaved nonlinear (e.g. BW or phase reserve dependent on output current) and this can contribute to the INL error. Depending on the input voltage the settling changes and the number of short times in between also changes (about linear with the voltage). So this effect can contribute to a U² contribution and thus the turn over error. The transient by itself would not be such a problem if they don't change - this would only give an offset, and if they extend over the short pulses maybe a little change in gain.

The good thing is that one can avoid this effect: With an added current to the integrator output, the transients look much better, even more than expected from the pictures shown  .
This is because the switching no longer includes the change in sign of the current and thus the cross over range of the output stage. The first test was with just a resistor for the extra current, the later solution would be a current mirror - this can even keep the currents after switching about constant. So things look good for using 20 K resistors for the integrator.

[Kleinstein]

Another short update:
The test with the 10 K resistors is kind of limited, as the gain is drifting a lot. Probably the more power type wire wound resistors are just not a good choice. With so much drift an INL test is difficult.

So back to 20 K (2x 10 K PTF56 resistors in series) at the integrator. This time with the current mirror to compensate for changing input current. In addition there is an additional capacitor at the integrator to improve the transients a little.
A test with disabled current mirror does not change much. So the main improvement is from the extra cap.

I did some INL test with an external, switchable reference:
The first one is the classical turn over test, this time in a fast version: the MUX at the input switches between 2 values and the ground connection is switched by hand.

The second test is using 2 voltage in series that give an about constant sum of some 9.3 V. This test can be done in 2 versions:
1) The more classical form with a zero measurement for auto zero of the ADC. There are 4 such readings (including one zero offset) that are repeated about 4 times. This test is symmetric about the center.
2) In a fast version, there are only 2 measurements:
 one is reading the difference between first partial voltage and the sum (some 9.3 V). The second case measures zero and the second partial voltage. The fast version is less sensitive to low frequency reference noise and thus attractive.
Ideally the two tests would give the same result. The 1st versions only adds 4 additional zero conversions.  However there are still some differences, especially from thermal effects and possibly from a delayed effect.

Attached are the results for the turn over test and the sum tests.
For the sum tests the + and x symbols are for the fast version using the normal and slow run-up versions. Likely due to thermal effects the curve is no longer symmetric.
The * symbol is using 4 separate AZ readings. By design this test is symmetric. These readings are more noisy as more steps are needed and thus more reference noise.

 

[Rerouter]

Sorry for the long delay, But I am back if you wish to continue, seems the current changes are slightly different choices in op amps, a revision on the input buffer, 2 arrays in series for the integrator, a canned oscillator for the micro and some change to the integrator response capacitors?

also provisions for the changeover input / multimeter functions.

[Kleinstein]

The changes done so far are:
1) slight changes in the input buffer (adding a resistor to provide a biasing current to keep the output stage in class A. 
2) A canned oscillator and for one of the 2 boards also 74HC74 flip-flops for syncronization
3) An additional capacitor at the integrator: a direct feedback for the "slow" OP
4) A low pass filter and buffer for the average integrator voltage - currently used for debugging, as a test-point.
5) For a test : add a current mirror at the positive supply, controlled by a resistor from the buffer output + one to ground. The current goes to the integrator output. As a result the waveform at the integrator looks better (no change with input), but there is essentially no change in the INL error visible.

There are a few planed changes, not yet in HW:
1) use different resistors at the integrator: either LT5400-100K (1 or maybe 2 in parallel) or NOMCA as 2x20K in series each
    this would be for a new board
2) test a buffer for the ground to the 4053 switch to make it easier to use an external reference
    I can test this with the current board.
3) For the integrator I would like to test another option to use extra FB from the average integrator voltage during run-up. This could help to reduce errors from DA and related. This part would be mainly an optional DG419 switch and a few resistors.
4) Changes to the buffer: 3 OP version with maybe different OPs or maybe just 1 AZ OP (e.g. OPA189).
5) Input amplifier and switching to make is a real voltmeter with different ranges, possibly later also a DMM with current and resistance ranges. This part would be more like a separate board.

The tests with different resistors, like 2x10K in series as the last version are more like for tests, to see if lower resistors are possible or if some INL contributes get stronger so they may be easier to identify. So far it is kind of unclear:   still need to check the INL with higher/lower resistance and otherwise same HW.

[Rerouter]

1) slight changes in the input buffer (adding a resistor to provide a biasing current to keep the output stage in class A.

I assume something like 100K to the -15V rail, or did you do something else?)

2) A canned oscillator and for one of the 2 boards also 74HC74 flip-flops for syncronization

Any description of how the 74HC74 is used, I presume inline with the PD2/PD3/PD4 lines? and maybe the PC3/PC4/PC5 lines?

3) An additional capacitor at the integrator: a direct feedback for the "slow" OP

would that be between U2 + and the intergrator input node, and assuming something low like 1nf?

4) A low pass filter and buffer for the average integrator voltage - currently used for debugging, as a test-point.

already have an integrator output test pad, so if you have a rough circuit, I will just add it. always been a chunk missing from that area I've not been sure how to fill.

5) For a test : add a current mirror at the positive supply, controlled by a resistor from the buffer output + one to ground. The current goes to the integrator output. As a result the waveform at the integrator looks better (no change with input), but there is essentially no change in the INL error visible.

Harder to visualise this, is this what you meant as a means to keep the buffer output biased on?

There are a few planed changes, not yet in HW:
1) use different resistors at the integrator: either LT5400-100K (1 or maybe 2 in parallel) or NOMCA as 2x20K in series each
    this would be for a new board
2) test a buffer for the ground to the 4053 switch to make it easier to use an external reference I can test this with the current board.
3) For the integrator I would like to test another option to use extra FB from the average integrator voltage during run-up. This could help to reduce errors from DA and related. This part would be mainly an optional DG419 switch and a few resistors.
4) Changes to the buffer: 3 OP version with maybe different OPs or maybe just 1 AZ OP (e.g. OPA189).
5) Input amplifier and switching to make is a real voltmeter with different ranges, possibly later also a DMM with current and resistance ranges. This part would be more like a separate board.

1. Had already started working towards 2 in series based on earlier comments, for 2 in parrellel that gets more interesting to lay out without cheating and mirroring on the other side of the board (you wanted the heat shared, which means to me all signals through both resistors)
2. Not clear why ground needs a buffer to use external references,
3. There is extra ADC pins, e.g. your peak overflow pin could be repurposed to this. as it would serve the same role to my understanding. if you have a circuit in mind, I will add it.
4. The buffer is the hard part, I know it will take time, so ready when you are.

[Rerouter]

Should also add, I finally discovered kicad has the hotkey of shift to select / deselect single items, so its even cheaper for me to move around chunks than before.

[Kleinstein]

The extra sync is for the PD3/PD4 lines to control the reference switches. The switch for the input is not that critical and does not need the extra sync.

The input buffer got a bias current from a 1-5 K resistor to the local bootstrapped supply (R87 in the plan), so a rather constant current.
The two boards I have soldered use slightly different versions of the buffer, especially the bootstrapped supply part and both work. The 3rd OP in the plan is an in loop buffer, so that the precision OP does to need to drive the load.

The additional capacitor (C14 in the plan) at the integrator is from the output to inverting input of IC11 (OPA1641 in current circuit). The current value is 390 pF, the best values depends on the other capacitors / OPs. So a values to be determined experimentally to get low overshoot. I don't think it needs a trimmer, more like one of 220, 330, 390 or 470 pF depending on the OPs and resistors used. With larger resistors at the integrator input the cap may be less important.

I have attached a circuit plan for my current planed version, both as PNG and eagle file (zip packed).  I know the circuit diagram is a little crowed.

The extra current mirror is with T5/T6 (below IC19) and the resistor values may still need some tweaks.


The choice of the resistors is a slightly difficult part and I have not decided for my board. I see several possible choices:
1)  1 x NOMCA 20 K with 2 of the resistors in series each. The reference part would be a 10 K NOMCA with 2 of the resistors in parallel each.
 This would be a good match to a LM399 reference, with still a little more noise from the LM399 than the resistors.

2)  LT5400 resistor: for the reference amplification a single 10 K version should be good.
    For the integrator one could use 1 x 100 K , 2 x 100 K in parallel  or maybe 2 or even 3 x 10 K in series. 20 K is a little on the low side, though it did work for the test with PTF56 resistors. 1 x 100 K would be a little on the high side, with slightly higher noise, but probably still similar or better than the 40 K NOMCA case. The parallel layout is tricky, but it should be possible, e.g. with the chips side by side and  references on the inside and only a single critical link. The 4 th resistor each would be a guard between the signal and the reference resistors. The nice point is that one can start with a single array and add the 2 nd later for lower noise.

An external LTZ1000 reference kind of needs better resistors than the NOMCA.  A LTZ reference with only the NOMCA resistors does not make too much sense, as there would be resistor excess noise larger than the reference noise. The LTZ reference could also need either a +16 V supply or a JFET instead of T7, to make it work with the slightly higher voltage.  The ground buffer IC1 in the plan would help with the external reference, as it would reduce the current spikes to the central ground point that would be at the reference. If not used one might need a 3rd ground line to the reference.

[Rerouter]

Would it be possible to upload your eagle schematic saved as the XML based format?

[dietert1]

Do you have some measurement or reference for your statement about "Nomca resistors destroy LTZ reference low noise"? Maybe some link?

Regards, Dieter

[Rerouter]

the 5400 series resistor arrays are pretty much the best you can get, and specced on only the worst case spec in there datasheet,

The nomca by comparison's typical value is about 2-4 times worse from memory,

Due to the position in the signal chain, most of the noise of the entire circuit is dominated by those input resistors, (was about 2700nV / root Hz when I was calculating using a 25K array), so using any tricks you can to reduce the noise of those resistors gets a very significant improvement in the entire circuit.

[Kleinstein]

In the thread about statistical arrays there was a report on added noise when using the NOMCA resistors to scale a LTZ1000 reference:
https://www.eevblog.com/forum/metrology/statistical-arrays/msg2527074/#msg2527074
In short: using NOMCA for a divide by 2 adds about as much noise as the LTZ1000.

Compared to the simple divider resistor excess noise is more of a problem in the ADC. Here the resistors see a higher voltage and more resistors are involved.
I see quite some extra 1/f noise. This could be either from OPA1641 OPs (3 pieces tested) much more noisy than normal or as the other main source from the excess noise of the resistors.  I also see the noise to go up when measuring the ADCs own reference - in this case resistor excess noise gets more important.
The data-sheet for the NOMCA specifies a noise index of < -30dBi. Using 2 resistors in series or parallel adds -3dB.  This is about the order of magnitude of noise that I see. So the resistors don't seem to be much better than the specs. There is a little hope that the 20 K arrays may be a little better than 50 K as there is the tendency that resistors at the upper end of the range can have higher noise.

In comparison the LT5400 gives < -55 dBi , so really good - kind of difficult to measure.

The TC and TC matching specs are also much better for LT5400, even though the NOMCA resistor TC matching seem to be often better than spec and using 2 resistors each also helps. Good TC matching can help with the thermal part of the INL.

Due to the position in the signal chain, most of the noise of the entire circuit is dominated by those input resistors, (was about 2700nV / root Hz when I was calculating using a 25K array), so using any tricks you can to reduce the noise of those resistors gets a very significant improvement in the entire circuit.

The resistor noise is a significant part, but not that bad.  For the Johnson noise the integrator resistors act as if 2 of them are in series to the input. The known OP noise correspond to some 40 K for the noise equivalent resistor. There is also some other noise, not yet full understood (e.g. from jitter and variations in charge injection).   The additional 1/f noise suspected to come from the  NOMCA 50 K resistors makes up about as much as all other noise sources together.

The resistor excess noise contributes to the normal additive ADC noise - this is not nice, but still not too bad, as the 1 PLC integration the frequency is still relatively high. So the additive ADC noise with a short is still good (e.g. still close to the spec limit for the 3458 at 1 PLC).
The more nasty part is that resistor excess noise also causes multiplicative noise - here the frequency is not limited to some 25 Hz from the AZ chopping. So the lower frequency resistor noise does matter and causes statistical variations of the ADC gain. This directly competes with reference noise. In this comparison the NOMCA resistors seem to be in between the LM399 and LTZ1000 reference noise levels.

[Rerouter]

Have what I believe to be all but IC16 done, also spotted an error in your schematic, IC4 is lacking a connection to the -15V rail

still have a few 2XX / 3XX references, mainly decoupling additions, and some references that I just cannot see clearly.

I was less clear with what you where doing with the resistor arrays with sets of 10, and around the reference area, so I took them as optional footprints, as such I tweaked what I had to allow parallel and series combinations, the reference one is done the same, just with 1 set to allow for parrellel. However If we stick with that, I will probably shift things around so the thermal pad would not short for any mounted on the backside.

Edit: There are some blue notes on the PCB, for noise and current, I have not updated most of them, so ignore for now.
Edit2: also revised most of the design files to use generic kicad footprints, so this one should preserve the 3D models for most next time I release an archive of it.

[iMo]

I proposed some posts back 2x LT5400-100k in parallel (thus you get 50k). You may then deploy 1x(100k) with LM399 (6.5dig) or 2x(50k) with LTZ1000 (7.5dig) when considering noise of the integrator resistors vs. Vref.

https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/msg2790476/#msg2790476

PS: put the package A on the top, the package B at the same place from the bottom of the PCB and wire in parallel via 6 vias. Easy..

PPS: randomly chosen new LM399AH will 1/f fluctuate within 1ppm (10uV) with some popcorn noise (4-7uV jumps) after 1500hours burn in, when lucky. So the integrator resistors value vs. 399 noise would be rather academical issue here, imho..

PPS2: the arrays around the 399 reference - imho - 1xLT5400-10k + OPA2277 (+/-14.1V Vref -> no problem with 100k/50k integrator resistors, afaik) is pretty enough considering the 399's qualities..

PPS3: ANY resistor wired to LT5400 in ANY way will make the entire TC worse (unless you own a bag of 0.2ppm/K resistors)..