For the adc, the design is similar to the one in the diy-voltmeter thread.
A difference is the integrator reset which is managed with another spdt 4053 mux, instead of being muxed through the main buffer/amplifier.
configuration -
ref lt1021/7V.
amplifier lsk389. will revert to jfe2140 as baseline, when get some more.
bench supply.
a biscuit tin lid covering the pcb helps to reduce noise.
The main column of interest is the last one,
10nplc noise is around 0.33uV RMS. 1nplc noise around 1.4uV RMS. I believe this is mostly from the adc input resistors.
reference noise in the adc, should most cancel, for a lo measurement/sample.
- sample ref-lo with no amplifier gain,
az 10nplc
> reset; azero on; nplc 10; himux ref-lo ; azmux ref-lo ; gain 1; buffer 30; trig
counts 10002 2022507 1977610 891 4000001 (lo) (hi -0.000,003,7V) (lo 0.000,003,8V, 0.000,003,7V) az meas -0.000,007,5V mean(30) -0.0000077V, stddev(30) 0.31uV,
counts 10002 2022490 1977610 232 4000001 (hi) (hi -0.000,004,6V) (lo 0.000,003,8V, 0.000,003,7V) az meas -0.000,008,3V mean(30) -0.0000077V, stddev(30) 0.32uV,
counts 10002 2022507 1977610 891 4000001 (lo) (hi -0.000,004,6V) (lo 0.000,003,8V, 0.000,003,8V) az meas -0.000,008,4V mean(30) -0.0000078V, stddev(30) 0.33uV,
counts 10002 2022490 1977610 229 4000001 (hi) (hi -0.000,004,3V) (lo 0.000,003,8V, 0.000,003,8V) az meas -0.000,008,1V mean(30) -0.0000078V, stddev(30) 0.33uV,
counts 10002 2022507 1977610 889 4000001 (lo) (hi -0.000,004,3V) (lo 0.000,004,0V, 0.000,003,8V) az meas -0.000,008,2V mean(30) -0.0000078V, stddev(30) 0.33uV,
az 1nplc.
> reset; azero on; nplc 1; himux ref-lo ; azmux ref-lo ; gain 1; buffer 30; trig
counts 10002 202317 197812 726 400001 (hi) (hi -0.000,009,9V) (lo -0.000,001,1V, 0.000,001,8V) az meas -0.000,010,2V mean(30) -0.0000071V, stddev(30) 1.28uV,
counts 10002 202317 197812 713 400001 (lo) (hi -0.000,009,9V) (lo 0.000,002,7V, -0.000,001,1V) az meas -0.000,010,7V mean(30) -0.0000072V, stddev(30) 1.41uV,
counts 10002 202317 197812 723 400001 (hi) (hi -0.000,007,0V) (lo 0.000,002,7V, -0.000,001,1V) az meas -0.000,007,8V mean(30) -0.0000072V, stddev(30) 1.39uV,
counts 10002 202317 197812 716 400001 (lo) (hi -0.000,007,0V) (lo -0.000,000,2V, 0.000,002,7V) az meas -0.000,008,3V mean(30) -0.0000071V, stddev(30) 1.37uV,
counts 10002 202317 197812 721 400001 (hi) (hi -0.000,005,0V) (lo -0.000,000,2V, 0.000,002,7V) az meas -0.000,006,3V mean(30) -0.0000071V, stddev(30) 1.38uV,
There is a -8uV difference when ref-lo is sampled from the himux versus the azmux - in az mode, regardless of nplc.
The ref-lo trace is kelvin sensed at the gnd pin of the lt1021.
The only adc count that changes (for 1nplc example) is the rundown count, so it is not a calculation artifact.
The difference is a bit large to be a thermocouple effect on ic pins/ or copper trace.
So I don't like this.
maybe switch charge-injection when the az mux switches between the lo/boot from the pc-switch to the ref-lo.
and/or distribution for different impedances of the mux paths?
But I still wouldn't expect this given that ref-lo is a low impedance input.
EDIT. Also if it was a charge effect on would expect to see the effect change at different nplc/apertures.
The other LO that is common to himux/himux2 and azmux is the star-lo.
So I should check to see if that shows the same issue.
Also there is the resistor R417 that can match/compensate the rds-on of the hi muxes.
for 10nplc no-az input noise is about the same as the az case.
> reset; azero off; nplc 10; himux ref-lo; azmux pcout ; pc signal ; gain 1; buffer 30; trig
counts 10002 2022490 1977610 228 4000001 no-az meas -0.000,004,2V mean(30) -0.0000038V, stddev(30) 0.34uV,
counts 10002 2022490 1977610 225 4000001 no-az meas -0.000,003,9V mean(30) -0.0000038V, stddev(30) 0.33uV,
counts 10002 2022490 1977610 232 4000001 no-az meas -0.000,004,6V mean(30) -0.0000038V, stddev(30) 0.35uV,
counts 10002 2022490 1977610 230 4000001 no-az meas -0.000,004,4V mean(30) -0.0000038V, stddev(30) 0.37uV,
There is a 3.8uV difference in non-az mode.
But this expected thermal variation (ref, op-amp Vos,resistors) from the calibration baseline point taken about 10-15mins earlier.