Analog frontends for DMMs approaching 8.5 digits - Discussions

[julian1]

I have a board which fixes some issues that interfered with testing.
Since the opportunity was there, the input section has also been updated/improved based on comments and suggestions.

Perhaps more important, there is now support to run automated self-diagnostic/unit tests, which are nice and quick to iterate through, and that don't require ad-hoc code deployment or instrument setup.

Being able to route precision voltages around the board using the board calibrator/ dcv-source, works really well.
And getting the test setup vector/ as well as expected-behavior managed programmatically, and locked down in code, is progress of a kind.

It is an interesting property that the input conditioning may be able to measure it's own leakage, and switching charge contribution,
And with different input dc biases.

With the tests in place, the analog switches can be progressively added, and change observed.

test method,
test05  charge cap to +10V. hold 10sec for cap DA to settle, then turn off/float primary himux switch inputs, and observe voltage. measurement is taken from boot buffer/opa140 output.
test06  same except use -10V dc-bias.
test07  same except 0V dc-bias .
test08  charge cap to 0V/agnd, let cap DA settle. Put a +10V test on primary himux input (pin 5), while it is turned off.
test09  same except use -10V on pin5.


- with two hi muxes (U413, U402) fitted.
test05    -0.5mV/10s. = -0.5pA.
test06    leave 5mins for DA to settle.  +1.7pA. 10mins. the same.
test07    5 mins for DA.   250uV/10s. +0.25pA.
test08    300uV/ 10s = +0.3pA.
test09    300uV/ 10s = +0.3pA.

conclusion - with just the adg1208 muxes, leakage is very controlled.


- add TI sn74lv4053 (U412) precharge switch, muxing boot.  AZ switch (U414) is *not* fitted.
test05    +22pA.  +21pA,  20pA.
test06    +23pA.  +25pA.  25oA,
test07    +17pA.  +20pA.

conclusion, a bit higher than might be hoped for,


- same test, as previous test except 4053 muxing signal.
test05    +20pA.
test06    +25pA.
test07    +22pA.

conclusion - 4053 switch position doesn't matter.


the 47p caps (C421, C428) are mlcc, and therefore a bit suspicious, but the voltage difference across them is very low.
board are well cleaned.
the copper guarding looks good to me.
the sn74lv4053 is salvaged from other boards, but that's because it had been demonstrated to work well.

I will try to add the previously shown AZ test modulation into the test suite- but am not sure charge-injection at ordinary AZ freq, will be evident above the leakage. I should probably re-review the previous 4053 tests, already posted to this thread. 

[Kleinstein]

The leakage currents without the 4053 fitted look really good. So the ADG1208 really seem to be good.  Even 20 pA with the LV4053 are not that bad, though we had hoped for less.

I don't understand the purpose of C430:  normally the signal to control the 4053 type switch should be a clean logic signal and not slowed down. One could even consider having an extra schmidt trigger like HC1G14 in front of the 4053 switch.  Depending on the control signal, the signal to the 4053 may also be a bit negative so that chip interal diodes start conducting despite of D409. This may lead to extra leakage. The input leakage my also be different with different inputs used.

[iMo]

I would pass all logic signals into the analog chips via 50-100ohm resistors..

[julian1]

C430 is my misunderstanding of an earlier comment, that this signal should be slowed.
I think I experimented in the past with a schottky at D409, to reduce possible negative voltages on the 4053 input protection diodes.
It is probably worth checking again.

For source-termination resistors, they may be an idea.
There is a little ringing on digital signals and 10-90% rise time is fast - 2ns measured with passive probes .
But the presence of quite a few control signals make it look more complicated than it is. 
And there is actually very little going on (by design) during normal DC sampling.


Does anyone know the input bias current of the 3458a (or other modern HP/Keithly) meters, on 10V/high-z range, with AZ turned off?

[iMo]

I would pass all logic signals into the analog chips via 50-100ohm resistors..

The logic signals are noisy even when stable at log0/1. And when chasing nVolts slowing the fast edges is good thing as well (the resistor's RLC and parasitic capacities create a low-pass).

[Alex Nikitin]

Does anyone know the input bias current of the 3458a (or other modern HP/Keithly) meters, on 10V/high-z range, with AZ turned off?

Here is what I have measured in the past for HP3458A and HP3456A (horizontal axis in Volts, vertical in pA), using  Keithley 617:

Cheers

Alex

[julian1]

I was trying to work out why leakage somehow got overlooked from the previous 4053 tests.
Those circuits had the possibility to trim the bootstrap/-ve rail offset relative to the input signal.
This was done with the intention to trim pmos/nmos charge-injection balance, but showed that switch leakage could be trimmed as well.

Looking at the data for lv4053, using ~= +-25mV offset, is enough to bring leakage into line.
So it is possible an offset had been inadvertently / accidently added when the measurements were done  ( data shows <1pA ).
Or maybe part variation, although that seems unlikely.

So it's possible to revert back to that circuit.
Or select another manufacturer's '4053, with lower leakage specs, but higher charge injection.
Although, after soldering, I notice there may be some some temperature dependency for 4053 leakage also.

Alternatively, Kleinstein's original proposal using discrete jfet/fet, and complementary driven capacitively-coupled charge-balance, with a low pF. trimmer cap, was nearly working in tests.
It appeared there was just a pcb layout issue, so that the control signal appeared to also be getting coupled to the signal. The advantage of the trimmer cap is that it can trim additional parasitic capacitance.
And it's probably a simpler circuit.

[julian1]

To summarize, I doubt I mis-measured the boot offset in previous tests - since it was some effort to generate - requiring a dedicated extra op-amp.
But it's hard to overlook that +-25mV offset could trim 20pA of the sn74lv4053 leakage, which is in the region of what the new tests show.
So perhaps there is something going on there.

Another possibility, might be to use both positive and negative bootstrap rails.
Then any 4053 leakage could be trimmed out with a resistor to the rail.
At least for the non-temperature dependent component.
But that seems a bit ugly.

The nice thing about jfets is that low-leakage (j201, 4117) comes out of the box as a datasheet value.
Then the charge-injection just needs to be balanced, with an inverted signal.
It just needs a good layout, whereby the very small trimmer cap is working in the range where it is effective.

Anyway doesn't matter for the moment, it's probably good to get the az modulation fixed up again.

[Kleinstein]

The leakage current from diodes and other semiconductors is quite temperature dependent. So the compensation is more from a diode than via a resistor. With JFETs it is common to have a dioded connected JFET towards the positive side as a compensation for a JFET switch turned off (it is actually 2 switched, as leakage it to both sides).

The -25 mV supply can be about enough to get the leakage of the neg. side diodes to about there saturation value. The effect can be quite nonlinear.

At least for an initial test the 20 pA leakage is not that bad. AFAIR the high end meters like 3458 and Fluke 8588 call for < 20 pA and other meter often only specify < 50 pA for the inputs.

[David Hess]

There are some rare JFET input integrated operational amplifiers which used input bias current cancellation, but they could rely on the matching of integrated JFETs.

It might be worth looking up the old ways of doing external input bias current cancellation.  Tektronix also did input leakage cancellation of JFET input stages in a few of their vertical amplifiers.

[Ole]

I do have a few ideas on cancelling out the Gate Leakage current on JFETs,
the easiest one, in my opinion, would be similar to the bias cancellation circuit in the Datron 1281.
Though that design has the problem of, if I am reading that correctly, the tempco of the leakage.

I have added a concept for cancelling the Gate Leakage current, though this would work best with close thermal coupling between the primary JFET and the Compensator JFET. Though this too would need to be carefully measured and adjusted to work ideally.

On another topic:
Concerning the AZ-Cycling I had the idea to utilise a 8:2 MUX (MAX329 or MUX36D04) with four phases, two of which being Zero Phases. Though this would be aimed at a differential front end.
The MUX36 could be problematic concerning guarding as its a TSSOP Part.

[Kleinstein]

Normally the gate current of the JFETs is not a big problem, it is low, at least at room temperature. Like with normal diodes the leakage current is not very dependent on the voltage (except for very low and very high voltages). So the obvious way to compensate if the leakage of another gate to the other side. As this is leakage to source and drain it would compensate for 2 JFETs switched off.
A nice point is that the temperature dependence is expected to be similar.

With just a single JFET one may not have to compensate and it depends on other bias paths if and how many diode connected JFETs make sense for compensation.

[David Hess]

Take a look at how external input bias current cancellation works using a second operational amplifier in the same package.  This comes up in single supply parts because single supply input stages cannot include input bias current cancellation, but it can be added externally with a second operational amplifier in the same package.

Since the input bias currents match for parts in the same package, the second amplifier is configured as a follower with a high feedback resistance which creates an offset proportional to the input bias current, and then the same resistance between its output and the input to be corrected adds the needed current for correction.  For scaling the feedback resistance could be made variable.

Tektronix implemented input bias current cancellation on their 7A22 differential amplifier using a pair of thermisters with one controlling offset and one controlling gain, so I guess there were two effects going on, or maybe that was for linearization.

[julian1]

Still exploring cmos switches for a bit,

Briefly for sn74lv4053a one difference with the previous tests - is the zener used to set the boot supply rail.
but tests show that a bootstrap supply rail between 4V to 5.5V doesn't matter much for leakage or charge injection.
Also tried another sn74lv4053a, purchased a few years apart from the one used for initial tests, but with the same result.
So i am not sure how to explain the discrepancy with previous test results.

Running az modulation. all muxes fitted.
DC accumulation on 10nF/ over 10s.

test14.
sn74lv4053a
+10V dc bais
1000nplc/off   20mV. 18mV.
100nplc/2s     17mV. 17mV.
10nplc/200ms   21mV. 22mV.
1nplc/20ms     35mV. 73mV.  70mV.   large measured difference. odd. but was definltey there.


But max4053 looks a lot better,
I almost wasn't going to bother re-testing it, based on past resulsts.
Identical setup as above - accumulation on 10nF/ 10s.

max4053
+10V dc bias.
1000nplc/off   0.3mV. 0.5mV
100nplc        0.8mV.
10nplc         3.8mV.   3.6mV.
1nplc          30mV.   28mV.

max4053
-10V dc bias.
leave five minutes for +4.5mV/10s. cap DA to settle.
1000nplc/off   2.5mV  2.8mV   - oct 8  2.3mV.
100nplc        3.0mV. 3.3mV   - oct 8.  2.3mV
10nplc         5.6mV.  5.7mV  - oct 8. 5.2mV.
1nplc          30mV   30mV.   - oct 8  29mV.

max4053
0V dc bias.
1000nplc/off   0.8mV.
100nplc        1.0mV.  1mV.
10nplc         3.8mV.  3.6mV.
1nplc          28mV.

leakage is more controlled -  <1pA for +10V and 0V, and <3pA for -10V dc-bias.

for charge injection
ie. 1nplc == 20ms.  10s/0.02s == 500 cycles.
this is 30mV / 500 == 0.06pC .
if I have the units correct, through full-cycle switch.

The above tests were done with the azmux held off, with only the pre-charge switch switching.
this would eliminate/isolate any leakage through the amplifer input jfets (if fitted) .


test15.
When the azmux also changed to for normal sampling between PC-OUT (S1) and LO (S6), the result is similar.

max4053
+10V dc bias
1000nplc/off   1.0mV  0.2mV.
100nplc        0.2mV  0.2mV
10nplc         1.0mV  1.2mV
1nplc          20.5mV.  20.5mV

max4053
-10V dc bias
wait for DA.
1000nplc/off   3.8mV. 3.2mV    maybe a little DA still from +10V test.
100nplc        2.5mV
10nplc         10mV. 10mV.
1nplc          56mV.  55mV.  56mV

max4053
0V dc bias.
1000nplc/off   1.3mV 1.2mV.
100nplc        1.8mV
10nplc         4.8mV
1nplc          38mV. 37mV.

Edit. add more data

[Kleinstein]

The data with the max4053 look good.
At least for 10 PLC mode and likely still with some 5 PLC the charge injection is good. For 1 PLC it may be an issue in a few cases, but would be OK too most of the time.
I am a little surprized that the charge injection / charge pumping depends so much on the bias voltage. The idea with the bootstrapped supply to the switches was to make the charge injection part at least independent of the external voltage. There may be an effect of the waiting time for the charge injection due to some DA or similar settling effect at the MUX / amplifier.

[julian1]

The charge-injection is is reasonably independent of dc input voltage, with just the PC-switch.
eg. at 1nplc.  between  28mV - 30mV from -10 to +10 V.
This indicates the bootstrap switching part is working,

But otherwise, I agree there appears to be a sensitivity to dc-bias when both switches are used together,

at 1nplc,   56mV (-10V) / 20.5mV (+10V)  =  a 2.7x difference
 

There may be an effect of the waiting time for the charge injection due to some DA or similar settling effect .

The previous tests used a 500us precharge phase.
When the precharge phase is increased from 500us to 5ms.  sensitivity to dc-bias is reduced.

  -10V bias.  1nplc.   38mV. 38mV.
  0V   bias   1nplc    30mV. 30mV.
  +10V bias   1nplc    25mV. 25mV.

  spread = 38/25mV = 1.5x difference.

So your insight/intuition looks right.

I think the magnitude of the charge-injection may yet be improved by following the original input discrete jfet scheme.
With a complementary signal, and small coupling cap/trimmer.

This could use a (maybe inverted) pc-switch signal, or az-mux or - perhaps a third control signal for more control.
but I would need to try think about what it would look like.

Edit. might be worth trying to bodge a 3pF trimmer from the pc-switch ctrl to the input node, just to see what happens.

[Kleinstein]

Adding some small capacitance to compensate some of the chanrge injection also with the CMOS switch may be an option (if the polarity of the control signal is right). Instead of a trimmer one may also use just a piece of wire getting close. This would more like a 0 - 1 pF adjustable cap.

A 500 µs precharge time is already not that short, but may be still OK. From another thread (3456 repair) I just saw that the HP3456 seems to use some 200 µs for the precharge phase.
For the difference in the input bias it is not some much the ratio, but the difference. With the short precharge time there are some 36 mV, corresponding to 36 pA average input current comparable to some 550 Gohm (looks negative ?) at the input. So it is not great, but also not bad. Still there would be the option to use a slower cycel when needed.

p.s.:
 I just got an idea for what could cause the extra current with a short pre-charge phase:  open, unused input at the MUX would be weakly coupled charge reservors that can act like DA ar a RC elelemt on the order of 3-5 pF and a few Tohms. So unused channels may want a defined (e.g. GND potential).

[julian1]

Some more experiments,

test15.
revert to baseline. 500us precharge.
max4053, 1nplc,
+10V   21mV,  21mV
0V     37mV.   37mV.
-10V.  55mV.   58mV.

I felt for-sure that tie-ing bootin guard (currently floating) to gnd would do something, by changing the capacitive loading on azmux out.
There is quite a bit of copper surface area and proximity. (this guard needs to wait for the amp to be populated to drive properly).
BOOTIN tied to gnd. also pin7 azmux instead of being left floating.
But, the result is the same.
+10V.   20mV
0V      39mV.  39mV.
-10V.   55mV   56mV.

remove cap C430. slowing pre-charge switching. - the same.
+10V    20.5mV.
0V.     37mV.  39mV.
-10V.   56mV.

tie-off unused azmux inputs (dci-lo, 4w-lo) to gnd. All azmux inputs are now defined.
no difference
+10V  20mV.
0V.   39mV.
-10V  57mV.

it is impressively stubborn, even to try and shift in a bad way/direction.

                       
Perhaps it's worth describing the algorithm. The guiding motivation is that whenever the azmux switches, the pc-switch should mux BOOT to protect the input signal. This gives the following sequence,

1. init/reset - pc switch to boot (to protect signal)
2. az mux switch lo -> hi (precharge phase, 500us)
3. pc switch - to signal. take HI measure.
4. pc switch to boot (to re-protect signal).
5. az mux switch hi -> lo.  take LO measure.
   goto 2.


I still think maybe it is not that bad -  if the magnitude of the charge-injection is reduced, it will also trim the difference.
But perhaps max4053 by itself, is still not the quite the right part.
         

[julian1]

max4053 seems more sensitive to the supply rail. Increasing the supply from 4V to 4.7V  increases charge-injection over baseline. 

test15. 1nplc. 
+10    31mV.  31mV.
 0       51mV.  51mV.
-10V  71mV.  74mV

The datasheet is characterized down to 3V single-supply. and suggests it can operate as low as 2.7V.
If I can find some lower voltage zeners, I'll try reducing the supply rail voltage.

[Kleinstein]

A reduced supply is indeed an option. In many cases the charge injection goes down with lower supply, For a more normal DMM the higher R_on not yet a problem.
Instead of a low voltage zener, one may also use a white / blue LED. The low voltage Zener diodes are often not that good (high TC and differential resistance) anyway.

It is interresting that a higher supply especially increases the charge injection when the input voltage in negative.

A parameter that one could try changing is also the small capacitors at the switch. Charge injection also slightly depends on that capacitance.

[julian1]

With max4053 supply at 2.70V.

1nplc.
+10V.      -12mV.  -12mV.            note negative .
0V        7.5mV.  7mV.
-10V.      26mV   27mV.

leakage is still controlled.

+10V   1000nplc/off -0.4mV
-10V  1000nplc / off 3.8mV.

But it is still a 26 - -12 = 39mV. difference. So the charge is the same, just the offset changes.

[Kleinstein]

The difference between the +10 V and -10 V case may not depend that much on the switch for the precharge switching. The max4053 does not see much of the change in the voltage, only maybe a different size current peak from charging the amplifier / ADG1208. The current peak may be effecting the supply voltage for the may4053.  Getting to some 7 pA input bias at 0 V is good.
Getting a more positive drift at a negative voltage means a positive input resistance (going back the zero), in this case on the order of 500 Gohm. This is OK, but not really great and odd that it depends on the time spend in the precharge phase.

The change of the input bias with input voltage may well be more a thing of the ADG1208 or the amplifier. These parts see the difference in the voltage. A small part (independent of the PC time) may be just leakage without the bootstrapped guards. Another part could be lossy capacitance and thus delayed charging of that capacitance. At least a part of this could improve when the bootin part is working.

[Kleinstein]

There is about an 18 pA change in the average input current from 0 V to 10 V. With some 40 ms for an AZ cycle this is some 0.72 pC per cycle.
One mechanism is lossy capacitance at the mux and amplifier input. FR4 material has a loss factor of some 2% so it would need about 40 pC or 4 pF at this loss level to get the 0.72 pC of charge flowing at the wrong time (e.g. with some delay). 4 pF of parasitic capacitance on the PCB and MUX chip package sounds plausible, depending on the layout. Ideally the driven guard traces at the mux and amplifier could at least reduce the effective capacitance.
Besides loss in the dielectric material itself there is also a chance to have partially isolated somewhat conductive islands (e.g. dirt spots on the surface) that can cause some "dielectric" absorption.

The current state with an effective input resistance of some 500 GOhm ( 10 V / 20 pA) is not that bad for a DMM. With a slower AZ cycle (e.g. 10 PLC) the change in the input bias goes down (nearly 10 x) and thus even higher input resistance. The inverse (= conductance) may be the better parameter to specify as conductance of parallel paths (e.g. leakage at the terminals, leakage at the input mux, charge pumping) adds up.

Not sure how other DMMs react with the 1 PLC mode - the 3458 prefers 10 PLC for highest accuracy and the specs are only for > 10 GOhm (not sure which mode) and thus not very sharp. I would not be surprised to also see considerably lower input resistance with 1 PLC than with 10 PLC.

[julian1]

The distance from azmux output trace to input amplifier jfets is short - only a couple of centimeters.
It is a six layer board, with two cores, and the trace is sandwiched on a dedicated copper layer between the two core (not prepreg) layers.

However the trace does cross a bunch of star grounds and some digital signals on other layers.
It is a weak point, but I considered it acceptable since there are no dynamic/changing voltages during sampling operation.
(the remedy if necessary - is to move the amplifier jfet placement).

But these gnd traces would definitely add to capacitive gnd.
Still it was surprising that manipulating the BOOTIN guard potential which has very close copper features, did not change behavior at all (good or bad).


At least it should be easy to test the loading - it is just a matter of lifting the azmux output-pin.

Edit. english
Edit 2. core not prepreg.

[Kleinstein]

Already as is the input resistance is not bad and with 3 PLC one would likely be already > 1 TOhm.
Chances are the curves shown earlier by  Alex Nikitin for the 3456 and 3458 are for 10 PLC as the default setting. I would not be surprized if at 1 PLC they would also show comparable or even more input current than the current PCB discussed here.

With a multilayer one can get shielding, but of cause the capacity also may get relatively large with only the thin layers.
A big difference may come up when bootin is actually driven as a copy of the input signal. Any other fixed level will not make much of a difference, though a floating copper part could be bad.
Driving bootin may be one of the next steps to try.

A relatively short distance from the mux to the amplifier is good - for some reason the old 3458 has quite some distance there.

A reduced supply voltage may also be an option for the LV4053 - though I would not unsolder the max4053 for this.