Analog frontends for DMMs approaching 8.5 digits - Discussions

[julian1]

Thank you very much for the detailed review and comments. To focus on the amplifier, as perhaps a major weakness.
I understand that bootstrapping jfets is conceptually equivalent to bootstrapping an op, while adding extra gain, and opening up options for suitable larger jfets.
JFE2140 are available. Leakage has the same spec as opa140 Ib - 10pA max.
How does one calculate the voltage gain/ CMRR contribution of the long tail pair stage?
And with parallel inductors across the source resistors, do the jfets become source followers, and gain collapse to 1 at DC? the jfets are in a common source configuration, with high voltage gain regardless.
Edit.

Scratch that. It's possible to simulate gain in ltspice in cascode configuration by removing the op and feedback, and inputting a small differential offset. 100uV. -> 13.15 - 12.98 V. == (13.15 - 12.98)  / 0.0001 == 1699x gain.

[Kleinstein]

The protection part ideally limiting the current in a linear way. So on overload there will be an essentially constant current, just enough to act against the rather small current (e.g. 5-10 µA range) from the PV OK.  At least in my setup it is not oscillating. The turn on speed should not be critical, I expect some 100 µs or so depending on the gate capacitance. The turn of part can be faster with some overshoot iin the current. Essentilly like discharging 2-3 x the gate charge. So far my plan is to detect overflow at the output of the main amplifier with a pair of comparators or similar (fast ADC in the µC in window comparator mode).

Calculating the CMRR for the JFET stage is a bit tricky. I see mainly 3 contributions for common mode gain:
1) The source side current source may not be ideal. A change in the current would translate to a small change in the offset due the mismatch in transconductance of the FETs.
    Chances are the matching in transconductance is good when the overall offset is matched.
2) Due to the Early effect in the BJTs the gain changes with there CE voltage. The difference of this effect between the 2 transistors will set overall effect. I still don't think one would really need the special LM394 matched transistors.
3) with a change in input voltage the power dissipation of the current source and the BJTs for bootstrapping will change. This can have secondary effects. In the sum the power would stay constant - so ideally these transistors could be kind of coupled and a bit seprate from the rest.

The long tail pair gain is relevant as transconductance gain, not so much as DC voltage gain. Here the bootstrapping part has essentially no effect. The transconductance should be  1 / (1/g_fet + R_s).
The GBW of the amplifier with the OP-amp is than set from the transconductance and feedback capacitance.
For details (e.g. the effect of parasitic capacitance and unequal capacitance on both sides a simulation is a good idea).
The inductors in parallel to the source resistors give extra gain for lower frequencies. 1 K and 680 µH gives a cross over frequency of some 230 kHz. This can help in getting faster settling without an overall super high GBW for the amplifier. It sould also help to get a high slew rate. The downside with inductors is that they tend to be non ideal and they may pick up hum - the use of 2 inductors could be to reduce the hum pickup if they are in opposing orientation.


The OP-amp after the JFET stage does not have to be low noise. There is plenty of voltage gain from the JFET stage. So in principle a TL071 should work. For a higher slew rate a TLE2071 may be a candidate. It helps if the OP-amp can work near the positive supply, as the CM voltage for the OP-amp is something like 1-3 V from the upper rail.

For the voltmeter part there is no real need for super low noise of the amplifier. The protection and other resistors aready give quite some noise. It would mainly be current shunts that can use a low noise of the amplifier. So noise wise there is no need to use the JFET2140. Because of good matching ( <5 mV is otherwise the premium grade) and low offset this could still be an option. Compared to other dual JFETs they are still relatively cheap, though there are other cheap ones too (e.g. SK2145).

[David Hess]

Scratch that. It's possible to simulate gain in ltspice in cascode configuration by removing the op and feedback, and inputting a small differential offset. 100uV. -> 13.15 - 12.98 V. == (13.15 - 12.98)  / 0.0001 == 1699x gain.

Simulation will not actually work to determine gain in a precision integrated design.  The open loop gain is limited by thermal feedback into the input differential pair, which is what distinguishes precision design, and why precision operational amplifier are not intended to drive heavy loads.  The highest precision designs even unload the output of the precision operational amplifier with some kind of buffer.

This is also why precision designs where thermal feedback would limit open loop gain sometimes elected to use a discrete precision input pair even though it seems like better integrated parts should have been available.

[julian1]

I think it's enough to get an idea/intuition of open-loop gain within an order of magnitude, based on the transconductance of the jfets and cascode npns (should use 1uV delta though, and compensate for circuit bias).
Output loading is just the jfet inputs of the op-amp.
With that said, I don't think open-loop gain is actually a useful figure, without feedback to tame non-linearity.
More important is CMRR, which if I understand Kleinstein's comment correctly is almost entirely determined by the up-front cascode stage (same for noise), and where temperature dependent non-linearity will come into play.

A suspicion is that some of the design complexity around the 3458a amplifier can be relaxed, if the fast sample/settle capability is not being optimized for - inductors and the variable current sink (more current, faster presumably).
Linearity can be partly checked with turn-over tests, and configuring with gain to also amplify non-linearities, and performing checks with low test voltages.

It is quite tempting to see what would be possible  with just dual/quad sot bjts, and thin-film resistors.
But perhaps a substitute footprint for SSM2212 as a modern matched dual npn would be useful.
I have never tried an ac analysis/bode plots in ltspice.

[julian1]

I have used a weak PV optocoupler to switch b2b dpak nfet gates at 500us/1ms. A bjt optocoupler has current gain and low base capacitance, so I could imagine an order of magnitude quicker response to short the fet gates (turn-off).

A question is whether the optocoupler b2b fet protection scheme could also be adapted to protect the ohms current source.

Positive OVC is handled by a diode. For high negative OVC, the common HP style is a chain of pnp bjts, with voltage drop across resistors used for turn off, but that becomes messy with discrete transistors. The output pmos fet of the current source is the part most exposed.

[Kleinstein]

Some of the Keitley (2001 and 2002) meters use PV Ok and a high voltage MOSFET in the current source.  Chances are one could use a similar circuit (maybe dep. MOSFETs ?) also for just the protection.
I don't see a big problem with the way HP uses the chain of PNPs for the protection.  The main down side is a somewhat larger voltage loss at higher current. With low currents in the low µA mauch of the current can bypass the transistors and less voltage is lost. A relatively high voltage is only really needed for low currents / high DUT resistance. So the voltage loss is not that critical as it may look at first.
With higher test currents like 1 mA and up it helps if the actual current from the source is reduced when the protection engages. Otherwise it take sizable transisors (maybe even TO220 case) to get a sufficient SOA.

Ideally current sources are made different for different ranges. The DMMs usually have quite a large current rance (e.g. some 0.3 µA for large resistors to some 1 mA or 10 mA for low resistors). This makes it somewhat challenging to get that with the same basic circuit, just swiching a few resistors voltages. So ideally one would split the current source to at least 2.
The parts to adapt are the switches and the OP-amp used in the regulation. The HP3458 for example useds an expensive DiFet type, that is good for very small currents, but not really good for the higher currents due to drift and LF noise.
The 34401 use a AD706 as a kind of compromise - not super accurate (especiall with low voltage across the current setting resistor) and also not great with sub µA currents.
Today there is the additinal option to use zero drift amplifiers in this place. They at least keep the drift part low, though they are not ideal for high resistance.

I have shown a reasonable well working current source in another thread. For the current source somewhat better resistors may be a good idea, but the basic circuit looks OK, a bit more optimised for higher currents, but still OK also for low current. For the switching much of the bias and leakage current can be seen as part of the source current. What matters is only the drift of these currents, not the current itself.
The 34401 type circuit is not that bad either. It allows for more voltage, but is a bit more sensitive the switch leakage.

How good the BJT matching needs to be is hard to tell. In the first approximation I get an about linear effect (e.g. CMRR on the order of 120 dB, about linear for 10% of  Beta*Va*Gm matching) from the early effect. So in that approximation only something like an 1 ppm effect on the gain, but not yet nonlinear. Chances are the nonlinear part is not that relevant as only a small fraction of it.
Another point is that the matching would be combined of the BJTs and FETs and resistors at the current mirror. Chances are the FET matching ( transconductance at a fixed current) would be the limiting part and not the BJTs. A similar, maybe worse effect could come from the PNP to provide the base current.

P.s. For the part of an linear effect from the early effect, I goofed up: I only calculated the linear part and thus only got a linear result  .  I think one would get another factor of 2/Va for the 2nd derivative, so something on the order of 0.01 ppm/V.  Still the calculation is crude and the model for the Early effect used ( beta = beta_0 (1+V/va) ) is not that accurately describing the real world.

[julian1]

For the pnps, HP use a dual canned pnp for the legs of the mirror, and a separate (would have poor temp tracking) canned pnp for the middle leg / npn bias.
It is such a useful/good mirror design (good for a discrete LNA also), that tests might be worthwhile.

[Kleinstein]

The 2 PNPs is the current mirror should not be relevant. They operate with an essentially constant voltage and current. The possibly problematic PNP is the 3rd one, that is in the extra can. Thermal coupling shoudl not be the big deal. The early effect of that transistor would give a modulation of the current to the long tailed pair. The current is not very high here, so less effect of a variation in the gain and also usually less early effect for low currents (this part is no included in the normal models/equations but known and visibe in the curves). On the other side there is no more effect of matching.

The effect is like this: with a more positice CM voltage the PNP sees less voltage and this way a reduced gain. The current source/mirror part keeps the emitter current constant and the base current is thus lost. So with the higher CM voltage less current is flowing through the PNP and thus more current for the JFETs. In addition the bootstrapping transistors need slightly more base current and thus an additional effect here too.
For the current source (if a BJT is used) there can be a similar effect: higher CM voltage leads to higher gain and thus higher output current. Here it could help to build the current source with a FET and thus no base current.

The amplifier in the R6581 uses a somewhat similar form of bootstrapping the JFETs drain voltage, but with an extra PNP as emiterfollower and thus slightly less loading of the source side. The effect should be comparable to the PNP at the upper current source, just from the other side and the base current directly. So nothing gained and possibly worse with a relatively high current.

Probably not because of the CM effect (but it could still help) the HP34420 uses a darlington circuit for the bootstrapping part and otherwise a similar configuration to the 3458.

The HP3456 and 3457 use JFETs for bootstrapping. Here at least matching can help. Dual JFETs with a higher threshold ( ~3-4 V) are rare - so one may have to use 2 selected singles here. So no early effect there, but an effect from the drain voltage to cause a small variation in the DS voltage for the main JFETs.

Some test or at least simulations could be worth it. Things get a bit tricky to calculate the old way.
There may be some similar research already done for highly linear audio (though many don't go to such details) or operational amplifiers.
A highly linear amplifier seems to be more tricky than originally thought.

[julian1]

How much is the magnitude of the channel effect in response to BC/CM voltage change, reduced by lowering current generally?
Are there any disadvantages in the darlington approach used by the 34420a - combined with a fet for the sink as you suggest?
I can see that it would not improve the centre leg bias to the npns but that source is already low current.
There are a lot of moving parts, it seems like more data would be useful to make sense of it all. 3458a seems to have done ok, without getting too complicated.

[Kleinstein]

The darlington approach could be a bit on the slow side, as it would ideally operate with rather low currents (even less than the 5.x µA in the 3458) at the input. It may still work OK with integrated darlingtons and thus small input side transistors. One loosed 0.6 V of headroom, which is probably still acceptable. I think somewhat reduced speed may not be that bad and I have an idea to make up some of it, at least for the cases with gain.

How much the early effect changes with lower current - I don't know. AFAIK the usual theory / models don't include this part, but they accnowledge that it gets better with relatively low current for the transistors. The spice models may in clude a slightly better approximation, but the quality may vary.  The known trend is that higher gain BJTs show more early effect. The relevant combination should be beta times Va (or could be Va² for the nonlinear part) and here I don't know. So it is not that clear if a higher or lower gain transistor would be more linear. From audio amplifiers there are sometimes arguments calling for not too high gain. 

The effect from the PNP and NPN pair should add up, both for the linear and square part. The current source part should add up for the linear part, but I think it may compensate for the square part, as here the collector voltage gets large when the CM voltage gets larger. It is still tricky with a NPN and PNP transistor working on quite different currents. Also I am not that sure the simple equation for the early effect is that accurate. So I have the feeling the BJT at the current source is a good idea because of that compensation.

The part that I initially thought of, is from the difference in the early effect in the NPN pair combined with the gm of the JFETs is only one part. A hard to estimate point is how good the BJTs (and JFETs) are matched.
Others are the low current PNP,  NPN at the current source and NPN pair base current. They give an additional change in the current to the differential pair. Changing the current to a differential pair changes the gain of the differential pair, but this would only be a change in the final speed and we don't care about ppm changes in the GBW.  A change to the amplifier DC response comes from the current effeting the offset and this is current change (that can be slightly nonlinear) times the difference in 1/gm for the FETs.  So this path also includes a matching part.

[Kleinstein]

I did a few simulations on the CMRR, to see how much the different transistors can contribut.
The idea with the simulations is to only look the the discrete build stage, loading it with a relatively small resistor. So no OP-amp and feedback.
The output signal is the current through that extra resistor (R1 in the plan)
With the current output one can use the JFET stage without the external feedback and this way easy apply a common mode signal (both JFET gates get the same signal)
This differential drive case gives the differential mode transconductance gain  (in my case some -50 dB).
The ideallized baseline configuration uses a P-MOSFET  instead of the PNP for the BS stage current. This eliminated most of the asymetry, though it may not be practical in real life.
The current source is with a N-mosfet. To include JFET asymmetry the right side gets a 10 ohm source resistor. I would consider this relatively large mismatch ( ~ 10% current and thus ~ 5% in g).
The ideallized baseline circuit gets a very good -202 dB CM gain and thus -152 dB of CMRR (difference to the -50 dB differential gain).
Tests are than done with one at the time PNP at the top, NPN at the current source and mismatch in the cascode pair.
With a 2N3906 for the PNP and 2N3904 for the NPN I get more CM gain for the BJT in the current source than for the PNP on the top ( -187 / -179 dB CM gain).  The size of the CM gain depends on the asymmetry in the JFETs - without the asymmetry (resistors) there is essentially no CM gain.
As already guessed both parts have the same phase for the linear part and opposite sign for the nonlinear part. So there could be some compensation, but not much as the effect of the current source seems to be quite a bit larger.  For the nonlinear part the CM gain at different offsets (+-5 V) is used.

The effect of mismatch of the cascode transistors can be relatively large, and it also happens without mismatch in the JFETs (2x5 ohm resistors) for the 2N3904 / BC547B pairing the CM gain reaches -164 db and thus SMRR of some -114 dB only. The effect is also DC voltage dependent and thus nonlinear.  A pair of same type transistors is likely better than the 2 different models which causes 18 mV in emitter voltage difference.  It still makes sense to get reasonable good matching in the 2 transistors.

In the old simulation file from Julian I found a rather slow response due to a likely faulty (GBW ~100kHz) model for the ADA4625. My LTSPice version is not up to date, so it could be fixed meanwhile.

[julian1]

The 152dB CMRR figure looks rather marvelous!

Using fets for the centre mirror and source, eliminates Early voltage effects modulating to the bias of npns with CM differences - compared with the bjt equivalent. And it eliminates the unbalanced current from the base of the middle pnp.

But I am not clear what the implications are for Early voltages on the other pnp collector currents. Maybe they are less important to the circuit?
 
The sensitivity to asymmetry can be helped with matching. If one can add resistors to unbalance the jfets for a simulation, then one could presumably add them to trim threshold mismatch in real life.

Ltspice incorporates Early Voltage in its BJT model, using the "vaf" parameter. Does the bjt model incorporate non-linear contributions derived from this variable also, eg. VA^2 ?

[Kleinstein]

The 2 PNPs in the current mirror see an essentially constant voltage (some 1.2 V collector to emitter). So the early effect is not an issue there.

The resistor works for simulating a mismatch for the JFETs because the simulation is open loop and not including the OP for the feedback. This way the resistor or a threshold difference causes a different current in the FETs and this than gives the mismatch in g.  For the CMRR it is not the threshold, but the g matching that would matter. In the closed loop case the resistor would only cause an offset for the input as the current mirror forces equal currents and the resistor could not compensate unequal g of the jfets. Source resistors a commonly used to trim the offset.

One could however trim the resistors at the current mirror to get / compensate for some asymmetry in the FETs.  There is however the problem for such an adjustment in the real world: the simulation has not problem with -200 dB of gain, a real world measurement has. It is hard to measure very low levels of CMRR, though it is possible (amplifier in x 1 mode and use a floating meter to measure the input to output difference).
The part for the JFET asymmetry the test is still relatively easy: change the the current (e.g. jumper at the current source, e.g. for a 10% higher current) and check for a change in the offset.

I know that the spice BJT models include the Early effect, but I don't know the exact shape used. The transistors operate with not much variation in current and it thus does not matter how the early effect depends on the current. This is more a thing for selecting the transistors, e.g. choice of BC847 (100mA) versus BCX54 (1 A) with maybe the hope for better performance of the large one. The nonlinear part of the CMRR is not because the curve (gain vs voltage)  for the early effect is nonlinear. Even a perfectly linear curve of the early effect would cause nonlinear parts in the CMRR, e.g. from 1/gain parts. So exact details of the early effect are not that relevant, the linear curve in the simple models is a good enough an approximation.

A P-mosfet for the current mirror base current is nice, especially for the simulation. In real world one would loose about another 2-3 V of headroom or need 2-3 V more of supply. Small low threshold p mosfets are not that common. It would still be an option. At least in the simulation the effect of the PNP transistor was not that large (137 CMRR) and it gets better with better JFET matching. I would expect the JFE2140 to have better than 5% g matching, maybe another factor or 10.
The current source seems to be worse, but here it is easy to use a FET with no obvious disadvantage.  With well matched JFETs a NPN can also be good enough.

[Kleinstein]

I did a quick simulation with JFETs instead of the NPN pair for the cascode. So a bit like in the HP3456.  This also works and does not look that bad. The nice point is that there is no more need for the Zener and extra current to the source side - at least not in the simple form.  A voltage shift could still make sense, as lower threshold JFETs may have better properties (less effect of the drain voltage) and are easier to get as duals.

It is just hard to tell how good the JFETs are matched when it comes to parameters like the output conductance, which is kind of corresponding to the early effect for a BJT.  Maybe worth a real world build of a buffer amplifier or test circuit to get an idea one how good the matching is.

[julian1]

  It is hard to measure very low levels of CMRR, though it is possible (amplifier in x 1 mode and use a floating meter to measure the input to output difference).

I am trying to think of an arrangement that would make it easy to test.
Perhaps having an adjacent battery powered chopper to amplify the input and output of the amplifier configured as buffer would be useful.
At least to a level where the 100mV range of a DMM could read it?
Then one just needs a way to sweep/offset the CM voltage.
Being able to trim the jfets (parallel resistors to the mirror resistors) to a low Vos would allow lots of gain to be added which might help.

 

[David Hess]

  It is hard to measure very low levels of CMRR, though it is possible (amplifier in x 1 mode and use a floating meter to measure the input to output difference).

I am trying to think of an arrangement that would make it easy to test.
Perhaps having an adjacent battery powered chopper to amplify the input and output of the amplifier configured as buffer would be useful.
At least to a level where the 100mV range of a DMM could read it?
Then one just needs a way to sweep/offset the CM voltage.
Being able to trim the jfets (parallel resistors to the mirror resistors) to a low Vos would allow lots of gain to be added which might help.

I have done it using a multimeter with microvolt resolution but Bob Pease discussed measurement of CMRR and Analog Devices published this application note.

[Kleinstein]

For just the offset of the JFETs a source resistor is better suited. The current mirror part would also effect the TC. So ideally one would avoid it. The JFE2140 starts with a low offset and likely no adjustment needed. Just for the JFET asymmetry the simple jump in current would be a good starting point, though this only effect some of CM gain contributions.

I checked the simulation for a NPN darlington pair too, with a little surprise. There is still an effect from the early effect, though the input base current is too small to cause this. It looks like the model used in spice not only has an effect on the base current, but also an effect of the collector voltage on the base - emitter voltage at a constant emitter current. So the change to a darlington pair does not help and more makes things worse, adding the 2 voltage effects. It only helps with the base current part.

The Early effect can be quite different for different transistor types. The general tendency seems to be that it gets smaller (Va larger) for  lower gain, higher voltage rating and higher CE saturation voltage.
A problem is that very few datasheets give the early voltage.  Some simple theories get a constant product of gain and Va for a given process (doping ?).
The SSM2212 has low saturation and rather high gain and may thus show large Early effect, though good matching.
If single transistors are used one may want to have gain matching to get matching in the early effect.

The bob pease article is interesting. One may consider adding parts to do the CM test with an extra FB setting. If the gain is set with an DG409 or similar one would have one more setting free and could use this for the test mode ( bob pease like).

[dietert1]

While looking at a Keithley 2182A nanovoltmeter i modded that 2182A with 5 to 12 Ohm source resistors to improve symmetry and stability against oscillation. The circuit is very similar to the schematic above, except it has four JFETs.
Then i ordered a bunch of JFE2140 to characterize them and make pairs of dual JFETs similar to the Keithley 2182A, with less than 50 uV offset voltage. Selected pairs should be a good method for near zero offset.

Regards, Dieter

[julian1]

Yes, the CMRR test function with FB gain, can be merged with normal amplifier operation function. Just need to jumper/break the supplies.

[Kleinstein]

I had some reading the effectiveness of the JFETs for the cascode part. The idea is that the FETs attenuate the variations in the drain voltage be a factor for g_m/g_os. The data are a bitt scattering but the factor seems to be around 200-500. At first sight this looks OK with the JFE2140 that calls for a rather small effect of variations in the drain voltage (graph with ~0.1 mV for 5-40 V VDS). This would suggest an CMRR of some 110 dB even without cascode. The problem is that much of this is from matching and when using less well matched JFETs for the cascode the matching no longer works that well.

So I kind of understand why HP swiched from the easy  2xJFET cascode to the more complicated BJT+JFET cascode. The BJTs have usually better matching  A few transistors directly give the parameter h12 = dV_BE/dV_CE and thus directly the attenuation factor for the drain/collector voltage. The BC847A gets some 0.00015 and thus 10-20 time bit better than for JFETs. In addion I would expect less scattering than with JFETs.  Besides the effect on the voltage there is also the more obvious early effect on the base current. Here the change in the base current depends on  gain times Early voltage and this combination seems to be much less scattering for transistors made by the same process. So the base current part can to a large part compensate. It still helps to have gain matching to indirectly get Va matching.

There are no direct data on the Early voltage of the SSM2212, but there is some information on h12, as Offset Voltage Change vs. VCB  (10 µV typ and 50 µV max) and this indicates very good matching. The high gain and good gain matching makes the current part also small. So the SSM2212 looks very good. The question is more if a cheaper transistor pair may work too. The JFET alone should have an attenuation of some 200 (tendency is better with low threshold) and the BJT about a factor of 5000. So this would allow 120 dB CMRR even without matching / compensation. With matched gain another 20-40 dB seems plausible. Just any transistor may not be good enough though.

Another effect similar to the Early effect is thermal nature: higher voltage causes more power and thus higher temperature and thus causes more transistor gain. Thus superimposed effect may explain why the data on the Early effect are not that commonly found in datasheets.  As a positive point one could thermally couple the BJT part for the cascode to the NPN or FET of the current source. The sum of the power consumption of the 3 parts stays approximately constant. So tight coupling would reduce the thermal effect quite a bit. Anyway the 3 should be a bit separate from the jfet pair.  The DMM7510 seems to have a SSM2212 outside the case with the JFET pair that is very likely used for the amplifier. Similar the Keithley 2182 has the LM394 outside of the shilding box.  With thermal coupling to the current source I would expect to get away with less distance.
To keep the thermal effects small, I would consider a slightly smaller current than in the 3458. The noise should still be OK / good enough.  A change in the current is anyway easy even later.

[David Hess]

The Early effect can be quite different for different transistor types. The general tendency seems to be that it gets smaller (Va larger) for  lower gain, higher voltage rating and higher CE saturation voltage.

Bob Pease also discussed the correlation between high Early voltage and low hfe.  It is not always desirable to have the highest hfe transistors.

[julian1]

The high gain and good gain matching makes the current part also small. So the SSM2212 looks very good. The question is more if a cheaper transistor pair may work too.

From a practical standpoint, there may be less benefit to cost-optimize the BOM at the margins, when costs are already dominated by hv divider and ref.
But having alternate footprints for baseline comparison tests and a minimal functional setup, with less dependence on part availability is definitely good idea.

There is a reasonable selection of npns for sot-23-6 duals.  HN1C01F (Ic=150mA), cmmx3904, cmx2222a, DSS4160DS (Ic=1A continuous) most of which I have in a parts bin.     
Two sot-23 in separate packages would be worse thermally, but might make picking pairs for gain matching easier.

The placement and cutouts for SSM2212 and LSK389 in the DMM7510 are weird.

[Kleinstein]

The choice of SMD duals is quite large, but only a few offer matching. For singles I would even consider TO92 with bend pins soldered to the SOIC8 footprint.
Some of the matched cheap ones come with odd pin out (FMBM5551 and similar) or tiny case (NST65011). The xxx5551 ones could offer a low Va due to the high voltage rating and relatively high saturation voltage. One extra foot-print could still make sense, as leakage at that point should not be that critical.

For the thermals I think it would be really worth it t couple the dual NPNs to the the current source transistor.

Some distance (well more than between the dual NPN and current source) between the SSM2212 and the JFETs makes absolutely sense, though I don't think it would need that much shield and cuts as in the DMM7511.

The really good matching of the SSM2212 mainly makes sense if the JFETs are also well matched. In many aspects individual matching alone helps relatively little. So the SSM2212 can not really compensate for poor FET matching and to a lesser degree the other way around.  The FET matching would likely be for gm at essentially the same current. Different from the threshold this may not no be that bad for JFETs of the same type. Similar some the BJT matching is about  gain * Va, and this combination also varies relatively little in a series.  Especially for the nonlinear part (the linear part is not that bad) it should be Va to the power or 2 and higher that enters. So good transistors to start with can do quite a bit, possibly even without matching. For the linear part is can be gain * Va that enters - so the choice of gain is less important, but for the nonlinear part less transistor gain and higher Va would be good.

Especially for the start there is no need to include the expensive divider and LTZ1000 (or comparable reference). Still  some $10 for the SSM2212 is not that bad if it avoids selecting parts.

[julian1]

TO92 directly on soic is a good for higher breakdown voltage. BCM847 are matched and inexpensive and follow the typical pinout. I ordered some a while ago but got sot-363 (very small!) by mistake instead of sot23.  But a sot-23-6 version is available,


  BCM847        VBE1−VBE2  VBE matching   2mV max.  (Ic=2mA) (nexperia)  (BS=sot363, DS=sc74/sot-26).  Vceo=45V.
  SSM2212      VOS 10uV typ,  100 μV max,  BVCEO=40V
  FMBM5551    VBE(on)(Die1) - VBE(on)(Die2)   -8mV  to  +8mV (atypical pinout).  Vceo=165V

[julian1]

Thinking about current measurement designs,

For input protection, 34401a and 3457a use a bootstrapped diode bridge to clamp current to ground during overload condition.
3458a is similar, except the top bridge diodes get replaced by switchable BC tied bjts, and there is an additional relay path to disable the shorting path.
I suspect this is to support a higher voltage/burden drop on the sense-resistors than two PN junctions would permit - in order to do ACAL 10:1 transfers between sense resistors.

[edit]
The other feature of the 3458a current section is the use of bootstrapped jfets across the higher value resistors.
So range selection is performed by shorting resistors to the input source side.
The jfet dRDS(on)/dDS is constant when on (shorted) because Vs=Vd=Vg=BOOT is constant.
The approach could also work using a bootstrapped cmos switch (eg. lv4053 + lm339 for control) if desired.

The more common ranging strategy, is to short to gnd the tap points between resistors to select ranges.
Perhaps the disadvantage here is the many open switches with voltage potentials creating opportunity for leakage - when selecting lower-current/higher resistor ranges where leakage matters.