Analog frontends for DMMs approaching 8.5 digits - Discussions

[Kleinstein]

For the BJTs there is no real need for tight VBE matching. So some +-10 mV should be OK and not effect the JFETs very much. The more relevant matching is gain matching and this way indirectly likely Va matching as beta*Va is about constant. The BC847 (at least the lower gain ones) seem to be OK though not great for the Va.
The sot363 is indeed tiny, but if really need one may still fit it to a SoT23-6 footprint

For the current ranges the easy way would be using relays for steering the current. Even good FETs have a hard time to beat the leakage specs, especially for higher currents.
I have a design for the current ranges that should be OK - maybe use a bit more powerful relay at the input and better shunts: the idea is using a classical chain of shunts and sensing from the top for the higher currents (down to some 1 mA FS range). The shunt resistance is still low enough to not add significant noise. The lower currents than uses an TIA amplifier. This way a single resistor / shunt can cover a wider range (fewer ACAL steps needed). So far this misses a bit on the low currents. If needed a 2nd TIA would be possible to than cover really low currents (this part is not really working on my PCB).
In my case the diode bridge does not need to be removed, as a 100 Ohm shunt is not working well with 10 mA anyway due to self heating.
The HP3458 has quite a lot of shunts in series to the sense path that add to the noise. This is not ideal for the higher currents.
The BJTs instead of diodes could be for lower leakage, but the difference is likely not very large.

[iMo]

My AD7177, LTC2500-32, ADS1263 together with the ADR1001 are nervously waiting in my drawer (not in my junkbox, of course) for the final AFE design you are elaborating here! Hopefully you will do it open source at the end! 

[David Hess]

For the BJTs there is no real need for tight VBE matching. So some +-10 mV should be OK and not effect the JFETs very much. The more relevant matching is gain matching and this way indirectly likely Va matching as beta*Va is about constant. The BC847 (at least the lower gain ones) seem to be OK though not great for the Va.

If Va matters why not add cascode transistors to make the collector voltage constant?

Also for what it is worth, I have found that for the same transistor and production run, the emitter-base voltage correlates pretty well with the hfe.

For the current ranges the easy way would be using relays for steering the current. Even good FETs have a hard time to beat the leakage specs, especially for higher currents.

My solution to MOSFET leakage in switching applications was to add another MOSFET in series to disconnect the drain or source and then drive the gate and disconnected drain or source to enforce zero volts across the MOSFET.  They do not leak very much with zero volts across them.  I did this in a high temperature application where a relay had to be replaced by MOSFETs.

[Kleinstein]

If MOSFETs are used for current stearing in for the current ranges, they don't see very much voltage anyway. Usually less than 150 mV spread over the 2 back to back fets.
With modern MOSFETs there is usually some protection for the gate voltage, from a zener diodes to source. This can lead to gate leakage - probably OK for many types, but the specs are usually quite loose. So one may have to check. Similar the low voltage leakage is expected to be good, but usually no sensible specs for this.  It probably works, as other DMMs (e.g. Keithley 2001 , 2002) use MOSFETs for range switching for the current ranges. A relatively large dynamic range for the current (e.g. 1 A at the upper end and some 10 µA full scale at the lower end) makes the switching quite a challange. It is not as bad as it seems at first, much of the leakage from the large MOSFETs for the high current would go the low value shunt.
I would consider the realy way just the simpler way.  Autoranging with current is anyway a bit tricky. One could also combine both ways nd used FETs for some of the smaller/intermediate ranges (e.g. 100 / 10 and 1 mA) only.  Using a TIA for the low currents also saves on the number of switches / relays needed, as a TIA could replace 2 or 3 normal shunt ranges.

The amplifier already use a cascode. Adding a 2nd cascode stage would be possible, but it would also come with downsides. The main one is that one would need another 3-4  V of higher supply and the OP-amp would have to work with that supply (maybe drop some 1 V). In the current, 1 stage cascode the positive supply already is at some 18-20 V to get good linearity up to +10-12 V. Together with some -15 V to get enough output range this is 35 V for the OP-amp. The TLE2071 / LF356 are somewhat limited in the supply. Even without a 2nd cascode stage, just a little more CE / DS voltage for the transistors can improve things.

Part of the problem is also from the base current - here a 2nd stage cascode would not make things better. An extra JFET stage would solve the current part problem, but at the const of reduced matching.
With BJTs to start one would still get the variable base current. Chances are the current part is the weak point.
From my estimates / simulation the combination of SSM2212 and JFE2140 should work OK with no problems - more like overkill from very good matching on both parts.
Here an extra cascode stage may even make things worse, disturbing the good matching.

For more normal BJTs and the JFE2140 things are not that clear, as the advanatge of maching gets reduced for both stages.
Similar SSM2212 and 2 separate not that well matched JFETs could also be tricky as some of the matching advantage is also lost - I don't known how much the parameters vary on non matched parts.
With just standard BJTs (e.g. dual BC547a) and JFETs (e.g. SK2145) it is not that sure one would get to the better than 0.1 ppm INL range for the amplifier.  With high Va transistors (the 5551 type or MJE340 may be candidates, though a bit large for my taste) it may work.

There is still the thermal part, but I think this would be OK, as the main part to worry is loosing the matching between the BJTs and these 2 also get equal power. A somewhat lower current would reduce the thermal effect (could be used for tests). The JFE2140 JFETs are quite low in noise - so even with a lower (e.g. half) current than in the 3458 amplifier one could still get comparable noise.

If one does not need super low noise, there would still be the option to bootstrap a full OP-amp instead of discrete FETs. In this case I would prefer the slower OPA145 (instead of OPA140 as initial amplifier idea)  to make things with stability a little easier. I have such a system with an AD8628 in my DMM version - it works, but the stability part is already a bit tricky and needs  pF range caps at the gain setting dividers. Extra protection may also add a little noise and maybe a few pA bias. I slight problem could be the settling speed.

[julian1]

For the amplifier, the basic function appears to test ok. Some notes,

- The protection schottky is removed. Since there is not enough drop for jfe2140 VGS at working current (0.74V). The ESD protection of the jfe2140 is used, with hi and lo are tied across the zener.

- The 100R across the cascode collectors/ op-amp input, indicated in the ltspice model,  is needed to keep voltages at the op input manageable.
    Otherwise the circuit locks up/latches at startup, and the op-amp output will saturate (probably through the ESD protection of the jfe2140).
    There is a question about loading the cascode collectors/op input with the 100R.
    the voltage difference is small and will equal the Vos of the op amp.
    But there will still be some current.  eg. op Vos=1mV, 100R, => Ir=10uA.  Albeit gain has already been added by this point.
    A future board revsion will add the option for ordinary anti-parallel diodes to the inputs.

- The extra startup current source is not needed for mirror start/ doesn't influence the lockup behavior, with or without the 100R.

- A pnp (3906) also fits the pmos (bss84) footprint for the centre-leg of the mirror.
    this makes it easy to test and compare bjt and fet approaches to the current mirror.

- Tested with lf411 and tl071a for op-amps.

  mirror pfet    bss84 -50V pmos.  60V.  have  smaller modern pfets but they are 30V.
  source nfet    bss138 nmos.   50V.
  cascode        bcm847 npn  . Ic=100mA,   VCEO=45V. (ssm2212 not tried yet.)
  voltage ref    soic-8 footprint. currently lt1021/5V with 10k/10k divider. can remove the divider when obtain a 2.5V ref (lt1019, max6190 etc).

  1.33V on mirror emitters.  1.95V on centre source resistor pfet.
  3.26V across the zener. (it's a 5.1V zener).

  1.31V Vgs on mirror pfet
  1.24V Vgs on source nmos

  Vos of jfets 7.3mV with lf411 (weird - very poor Vos or Ib of lf411 ?).
  4.6mV jfet Vos with tl071a and pnp for mirror.
  4.9mV jfet Vos with tl071a and pfet for mirror.

- it would be nice to have a scope with integrated sig-gen for automated bode plots. With amplifier configured a buffer, and a square wave input, there's an overshoot that is corrected in around 5us.   

For cmrr test, the plan was to use a +-18V bench supply for the amplifier, and power the board and auxillary op-amp, with a spare 34401a transformer + regulation.
lm78xx/79xx were chosen for regulation which are rated to 35VDC input.
But the 34401A transformer outputs 37-38VDC after rectification/filtering (Should have measured it, before committing to a design!).
lm317/lm337 could be bodged, but a new board will fix some other issues also.


The optocoupler/ b2b fet protection scheme looks ok. At least for +-100V over-voltage, using 200V to-247 fets, the fets shut off in around 500us-1ms.
There's a pcb routing error with a hv trace cross, with only pcb prepreg separation, rather than using the full pcb core thickness, which needs to be corrected.

[julian1]

Hmmm, I am now thinking the measured voltage across the zener is wrong, and it should match the rated voltage.

Edit. scratch that. A 5.1V bzx84 zener at 22uA (6.3V/over 220k) drops around 3.7V, so the in circuit value of 3.26V looks about right for 8.7uA. (2V drop on 230k source resistor).

But perhaps a zener with better temp stability should be preferred. ie. 1n750 for ltspice model.

[Kleinstein]

A relatively low votlage for the zener is normal and wanted. A weak point of the cascode amplifier is that one needs quite a bit of voltage headroom. It makes sense to get the voltage over the JFETs down to some 2 V, not to loose too much voltage there. A voltage higher than some 4-5 V may also increase the JFETs 1/f noise. Less heat from the JFETs is also a good thing.
The lower TC zener diodes are for a higher voltage, usually some 5 V for a bare zener and more for the compensated. If used with a much lowe than normal current and than a lower voltage even the low TC zener diode would show a negative TC. A negative TC in the -2 mV/K range (to compensate the casode transistors) would not be bad, but porobably also not critical. After all the JFETs are matched and could suppress a slow change in the drain voltage and this would only effect the offset drift. Some 3.3 V for the zener looks reasonable, slightly on the high side, but perfectly OK for a first test.


I don't see a reason for loading the OP-amp input with a resistor. This would invite a stronger effect of the OP-amp offset. So with a resistor an effect of the OP-amps offset would be no longer surprising.
If at all one could consider an RC series element as an option to trim the frequency response.

A relatively large effect of the OP-amp on the offset is surprising. The OP-amps offset should not have a significant effect on the current balance. This would be only rather indirect via the early effect on the transistors (mainly the current mirror).

The rather large TO247 case for the protection MOSFETs would mainly make sense for the creepage distance, but hardly with 200 V MOSFETs. The more obvious choice are relatively small (e.g. TO251,TO252) case MOSFETs for some 1000 V  (e.g. STU2N105). Small FETs also help to speed up the turn off part and keep leakage low. 500 µs looks like rather slow for the protection to engage.

[julian1]

I made a mistake with the inductors in the initial ltspice model - at least in reference to the way the 3458a amplifier does it.

The inductors don't parallel the source resistors of the jfets and tie at the common zener anode. Instead the inductors are in series (ie. behaves as a single inductor) and it shorts the two jfet sources directly at DC.

I suspect that by always keeping a voltage drop over the jfet source resistors even at DC, there is a better local negative feedback effect (like an emitter degenerator).

Temporarily removing the inductors cures the instability/startup issues I was having. The amplifier now starts and is stable -10to+10V and from DC to 1Mhz at unity gain.

It is curious that the 34420a has an analog switch placed to short the jfet sources in a similar way - although I suspect the reason there is more for cal/offset adjustment/ thermal walk.

For the optocoupler/b2b fets, I was using DPAK, but then noticed the VAC spec of the 3458a, and thought it might be interesting to try for as an experiment. But, I now realize there's not enough amplifier headroom for Vpp, anyway after the hv divider. So reverting back to DPAK is reasonable.

During a hv excursion there is plenty of current through the opto driver leds. It's more a case of being fast enough to stay under the instantaneous/non-continuous led current handling specs of the optocoupler.
So probably a higher output current is needed, rather than gain, for faster fet switch off.
I've changed to use a small bridge rectifier to allow for a uni-directional darlington optocoupler, and also added the option for an extra discrete bjt.

[julian1]

The amplifier is also stable with a 1mH (replacing two series 680uH) placed at the two jfet source pins (before the source resistors) following the approach of the 3458 schem.

[Kleinstein]

There is not much difference whether the 2 inductors are directly connected to the source resistors or not. It is mainly about having the source resistors in series to the current source. So the slight unclear point in the 3458 schematics (is there a dot / connection or not) should not make much difference. My assumption fur using 2 x 680 µF instead of 1.5 mH is that with 2 inductors oriented the opposite way one could reduce the sensitivity to an external magentic field (e.g. mains hum).
For the inductors the details (resistance, Q factor, self resonance) could make a difference - inductors are often not that ideal.

The switch parallel to the source resistors in the 34420 is there to change the input stage gain with the overall gain. With the switch closed the input stage gain (tranconductance) is high and the noise is reduced. However with this the amplifier has too much GBW to be stable at low gain. So with an low gain (1 and likely also 10) the switch is opend. The additional noise is not yet a problem at low gain. Slowing it down all the time (larger capacitor at the OP-amp) would have slowed down the cases with high gain (e.g. 10000) too much.

For the input protection using smaller MOSFETs results in a lower gate capacitance and thus less time needed to turn off. Another point could also be the current used to drive the PV optocoupler. Here one may want to keep the current low and maybe have a series resistor, as the photodiode can store charge similar to the reverse recovery effect of a very slow diode. A photodiode wants a long storage time to get good efficiency. I have not actually tested my protection very much and I am a bit reluctant for a hard stress test, as the input amplifier has so little input bias.

edit:
 I did a quick check on the time needed for the protection to engage: With a rectangular signal of -10V / -20 V the protection needed some 2-3 µs to engage. It is a bit unclear how much the additional transistors contribute. Chances are the transistor part can be even faster and the 2 µs is than the point when the optocoupler part takes over.

[julian1]

The use of series resistance to create a drop across a bjt emitter, to pull the fet gate gates, looks like a superior design.
The advantage being that it can engage before the optocoupler.
A resistor to reduce the PV capacitance seen by the bjts/optos also looks like a sensible addition.
 
https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/msg3827432/#msg3827432
https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/?action=dlattach;attach=1328909

[dietert1]

Better make a separate test setup for the protection circuit - i mean with a load representing the amplifier input (e,g, clipping diodes plus capacitor). You will see that the original circuit with a current limiting resistor and two additional npn transistors works better to quickly discharge the gates. Each npn transistor should get a 1K resistor in front of its base in order to limit base current at some mA.

Regards, Dieter

[Kleinstein]

I totally agree that it would help to have the extra transistors. They may speed up things with rather fast transients and they would add a fall back option in case the opto-coupler would fail.
For the base reistors 1 K would be rather high, as the voltage should be rather low - maybe more like 100 Ohm.
Ideally the inductor on the input side should slow down transients at least a little. 1 mH and 1000 V would still give 1 A/µs.

A separate test setup for the protection is a good idea - not to damage / stress the amplifier and also to have a better way to measure the current on the clamp side .

[julian1]

Thanks for the comments. The way board makers now provide several boards per order makes it easy to selectively populate a dedicated pcb to test bits in isolation. I've done that already, for the very modest basic function test.

I previously made an assumption, that a small latching relay can switch beyond rated max voltages (eg. EE2-3SNU-L  220 VDC, 250 VAC), so long as it switches (open or close) into a high-z node (such as the 10Meg divider, or turned off p2p fets) and there is no carry-current.

And that this is one of the advantages of using the b2b fet scheme - one can use smaller relays, because the b2b fets work as a second switch that can be sequenced with the relay.
 
But I am now wondering if that is correct. A previous schematic revision used hv coto 5503, in parallel with a small gold lead relay for a low thermal/thermocouple offset. But the Coto is big and unwieldy, and it needs a lot of current, something like 100mA from memory even if it only needs to be turned on temporarily, before the smaller relay is engaged. A parallel b2b fet/ssr cannot replace the relay, following this scheme because of leakage.

Is anything known about using latching relays outside their maximum switching voltage - when the relay is just switching into another switch/ or high-z resistor?

[julian1]

Actually Meder  SHV05  andLI05-1A85, hv reed relays are a better form-factor than Coto 5503 for the initial hv contact make or break. That is, iflower-rated latching relays cannot be used directly with restricted condition.

[Kleinstein]

I don't see a probelm with using a relay with a lower voltage rating in series with a electronic switch (e.g. b2b MOSFETs with PV drive or a photomos switch, which is essentially the same in 1 case). The capacitance and high resistance (Gohm range) of the open electronic switch do not allow for the contact voltage to rise very fast. So for the short time to actually open the contact the voltage will be low and later on the open contact to contact rating would be relavant, no longer the switching voltage rating. When closing the relay it is only the relatively limited capacitance (a few 10 pF) to discharge. Even with the path to the 10 M divider, the current is limited by the resistor and I see no chance for a standing discharge with 10 M in series. In addition, at least in my version I have 2 contacts in series for the divider.

Especially for the initial version and tests a high resolution DMM would not be made for a harsh environment with large spikes and aiming for a CAT 3 or even just a CAT 2 600 V rating.
There are compromises between input protection and noise. Additional protection elements (e.g. PTC) may also add thermal EMF. In my relatively crude test a PTC did not show significant thermal EMF, actually better than some resistors.

AFAIK the impit protection of the Keithley 2002 uses a likely fusible relatively large form factor resistor and 2 back to back MOSFETs (no extra BJTs for an extra turn off) and the same clamping to an optocoupler idea. For some reason there are 2 added diodes and what looks like a zener diode. I don't know for what reason, as most modern MOSFETs include a zener diode for the gate and the PV optocoupler can also sink current (~16 forward biased diodes in series) when the voltage goes higher than some 12 V.

[David Hess]

A relatively low votlage for the zener is normal and wanted. A weak point of the cascode amplifier is that one needs quite a bit of voltage headroom. It makes sense to get the voltage over the JFETs down to some 2 V, not to loose too much voltage there. A voltage higher than some 4-5 V may also increase the JFETs 1/f noise. Less heat from the JFETs is also a good thing.

Robert Pease mentioned discovering that high drain voltage also increases gate leakage.  He initially thought it was something new but it was a previously known albeit obscure issue, caused by impact ionization?

The lower TC zener diodes are for a higher voltage, usually some 5 V for a bare zener and more for the compensated. If used with a much lowe than normal current and than a lower voltage even the low TC zener diode would show a negative TC. A negative TC in the -2 mV/K range (to compensate the casode transistors) would not be bad, but porobably also not critical. After all the JFETs are matched and could suppress a slow change in the drain voltage and this would only effect the offset drift. Some 3.3 V for the zener looks reasonable, slightly on the high side, but perfectly OK for a first test.

I am sure I have seen some bootstrapped JFET designs where a constant current through a resistor was used to bias the bootstrap transistor to follow the JFET source.

[Kleinstein]

The dependence of the gate leakage current on the drain voltage is shown in some data-sheets. I would not consider this an obscure property, more a point that is not very often relevent as the current is still small. Impact ionization or hot electron effects (electrons with higher than normal energy, so not in thermal equilibrium with the crystal) are definitely candidates for the extra gate current and also for the 1/f noise.

A simple resistor to set the voltage for the bootstrapped cascode is definitely possible - the typical circuit aready has a relatively constant current. There is still a small change from the early effect at the current source / current mirror.  For highest linearity one tries to keep the voltage constant. A simple zener diode is not much more effort than a resistor, but reduces the variations a little, even if the zener at a few 10 µA is far from perfect.

[Ole]

Hi there,
I was looking up different op amps to use as the primary op amp in the input amplifier here are some of my options:
OPA140(with asymetric supply voltage)
AD4625
MC34081
OP-27
What are your opinions/recommendations for the primary op amp?

Edit: I looked into the ADHV4702-1 and I think its interesting...

[Kleinstein]

The amplifier after the JFET front end is not that critcal anymore, as there is gain from the JFET part. So the noise and offset drift are not that critical.  It helps if the amplifier has a common mode range that extends relatively far up, as the output signal is relatively close to the upper supply (e.g. some 1-2 V from the positive supply).
So the OPA140 and AD4625 are not needed and the somewhat limited common mode range is not good.  The OP27 could be OK (though limited SR), but more overkill and also not good with the common mode range. AFAIK the MC34081 is obsolete.  I would consider an TLE2071 / TLE2081 if a high slew rate and GBW is wanted.

If the amplifier uses an additional stage for the output, to make it an compound amplifier, one could also get away with a slower amplifier, like TL071 / LF353. The output stage would than give the extra speed for the cases with gain. 

[Ole]

Over the last few days Ive looked around and found two candidates
that have significantly lower noise and could fit even into the front end of the 34420A:
The ADA 4099 and
The ADHV4702

In my case the 4099 would be supplied with +24V/-18V and the 4702 would be supplied with +-40V (I happen to have these on hand)

Cheers, Ole

[julian1]

Here's an initial Bode plot for the discrete amplifier without any inductors.

The amplitude is 20dB down, due to a 10x probe used for the DUT output.
I cannot see how to configure it from 1x to 10x in the Bode analysis menu, or even if it's possible.

Using 1x loading (minigrabbers into bnc) the amplifier oscillates, presumably due to capacitive loading of the op-amp output.
There is a 500R at the non-inverting jfet input. I should probably match it with another 500R after the op-amp, to simulate the RDS(on) of the feedback gain switch. Then the DUT/op-amp could be probed after the 500R.

The only compensation is a 100p for the tl071 op-amp. Need to review this again - can possibly be removed, or reduce to 20p.

Edit. Ok figured out how to setup the 10x probe.

[julian1]

Ok, 22p is not enough and the tl071 wants 100p compensation for stability. There are footprints for series RC to the inputs, that could be tried for compensation. But a faster op with more phase-margin might be interesting to try.

Here's two plots, first without an inductor, and second with 1000u in the same fashion as the 3458a. I goofed up the footprint for the inductors, which so the pads extend into the guard (they worked fine with silkscreen). 

 

[Kleinstein]

It is strange to see a litle more gain at the higher frequencies with the inductor.  I would have expected the inductor to reduce the gain at higher frequency. That is if a short is used instead of the inductor. Compared to just the inductor not polulated the added inductor would add gain at low frequencies.

The drop in the gain already at some 50 kHz is anyway strange.
Normally the compensation needs 2 capacitors: one to the postive supply (or ground)  and one in the OP-amps feedback.
Can you post a schematics for the circuit used ?

[julian1]

The amplifier has a 0R at C508 to test with unity gain. Only a single 1000u inductor is used (connected as indicated in schematic without junction).