Analog frontends for DMMs approaching 8.5 digits - Discussions

[branadic]

Would be great to design, as a POC, a simple +/-12V input front-end only (capable say 7.5digits). It will satisfy 90% people here, as most of us want to measure their references only.

If that's the way you are comparing references against each other you're doing it wrong, as you completely rely on your meter, its reference, input path and linearity. Measuring the difference between two references in the lowest range of your meter is way more sufficient.

-branadic-

[iMo]

You do not need to have a 7+ digits capable meter for comparing two references. A single opamp null meter will do it  Anyhow, the first thing people need is to measure the references absolute voltage, imho
And people do it as you may see from the graphs published for example in this section..

..Measuring the difference between two references in the lowest range of your meter is way more sufficient.

[Echo88]

All good points Kleinstein.

Offset/Bias-compensation might be not neccesary here as you point out when using a low offset JFET, thats why it was so only added as suggestion.
Youre right about U5/9/3/6 being unnecessary.
I kept U9 behind the TLE2081 (the 3458A Black Edition uses it, good guess with the TLE2071  ) to avoid thermal load feedback of the TLE2081 to its input transistors, though the 3458A apparently works just fine without it.
The TLE2081/AD8065-stage might need correction.
GND-Compensation-OP can indeed be generic.
U12/13: 125pA bias * 5kR = ~10nV, i dont know if id trade that with the offset drift of the OPA141...
Changed RN2 to lower resistance 460R variant, which is also available. 1k might also be useable, id need to calculate noise contribution.
Can you suggest a 4:1 low leakage Mux? Seems to me alternatives like TMUX6111/TMUX6136 arent much better?
Good point on the limiting resistor in the composite OP stages, was a little worried about them before.
Changed JFET-stage current to the original value from 3458A: 1.78k which equates to 1.4mA and therefore 0.7mA through each JFET/BJT.
I added the changes and suggestions which JFETs/BJTs were assumed used in the 3458A black edition, these details/photos are also available on xdevs as linked in the schematic

Can you expand on your reasoning why the RN6-network isnt suitable compared to PRND? Are we talking about an influencing power coefficient here or other errors?

I wont go for a 5V-range with this design.
While it will benefit from gain-stage-avoidance and therefore have very good specs, it still feels half assed.
If the gain stage really needs better networks than TDP1603 im willing to go that way if necessary, i just want to avoid such costly stuff were its not necessary.

I attached the revised schematic.

[miro123]

It is nice to look at open source HW development
Everyone has the freedom to choose own architecture design en implementation.
Here my remarks over current schematics
1. Cascaded opamps has no purpose here. They are used to mitigate HF ADC SC spikes. 
2. R15 R16 1K - to high. It is related to my previous remark - they completely decouple the ADC from the driver
3. Are you planing to use ADC on different board on your final design?
4. ADA8265 can be susbstituted with opa525 opa2625  /if needed/
5. how you gonna achieve thermal coupling with TDP  resistor networks - old school DIP package does not offer thermal connection. No therlaml bridge  e.g.  LT5400
6. Where is the auto calibration circuit? Do you plan to use autocalibration? If yes what type  - gain ,offset, linearity or all of them

Personally I will stick to HPM7177 architecture - differential input AFE
1. Differential inputs easy the PSU requirements.
2. lower Thermal EMF lemo connector - simple physics - lower dT -> lower EMF
3. lower EMC issues due to the twisted pair shielded cable. Applicable in modern world where we are surrounded with noise from 50Hz to 6GHz


 

[Kleinstein]

The RN6 network at the single sided to differential stage sees quite some power and this will cause thermal INL problems. 4 K and up to 12 V would be 3 mA.
To keep the power at a reasonable level one may have to use more like 10 K values and even than it may be a possible source for an INL error (depending on the TC).


For the gain settings the TDP networks should be good enough, at least linearity and noise wise. For the long term stability the data-sheets are often not very specific. Part of the problme is that there is one DS covering a large range of resistance values. Chances are that things are better in a more moderate range (e.g. 10 K ) than for the extremes (100 K or 100 ohm). Long term drift specs are anyway tricky - who knows how a part really reacts to years of aging and real world thermal cycles. Accelerated tests are somewhat limited.

The cascaded OP-amps have multiple purposes, sometimes just one is enough justification:
1) high frequency spikes
2) remove the thermal load from input stage
3) reduce the loading effect on INL (output cross over)
The 2 OP buffer stages may need an extra resistor in the FB to the AZ amplifier. Otherwise the 100 pF are quite some load to the fast OP-amp and may cause instbility.
Anyway - these are the stages that may be skiped anyway.

The U12/U13 part does not need to be low offset / low drift. There drift compares to 10 x the JFET stage drift and is corrected with the AZ cycle anyway.

For a low leakage 4:1 mux, there is the MUX36D4 as a close relative to the 36S08. The 2nd half would than just stay unused. the 4:1 mux chips often come as 2 pole ones.  Analong has the ADG1209 and there are probably more to choose from, many even with the same footprint (if same case).

[Echo88]

@miro123:
1. like Kleinstein said, cascaded OPs which drive the resistor networks are used here to avoid thermal feedback in the AZ-OP due to changing load current, which would decrease their excellent specs
2. correct, directly connected to an ADC this part needs to be changed a bit anyway for CM/DM-filtering depending on ADC-type
3. this frontend is intended to be used later with AD7177-2 and AD4030-24 ADCs, all sitting on the same pcb and thermally stabilized like in the HPM7177
4. yes, in this case the ADA4523 are used due to their excellent CMRR and Avol-specs, to minimize their error-contribution. The OPA2625 can drive the ADC directly, but its not suited for this task without working in a cascaded OP-stage due to its worse specs.
5. TDP1603 are used since:
-DIP-package which reduces mechanical strain from pcb-TC/humidity swelling and therefore changing resistor parameters
-8 available resistors allowing many dividers combinations
-proven in stuff like Wavetek/Fluke 7000 reference, CERN PBC 10V/10mA source (assumed due to paper)
-noise-spec was tested by Nikolai Beev
If further thermal coupling seems necessary that is no problem by usage of thermal jumpers. The TDP1603 dont need to be thermally connected to each other, the design was done so that every divider is consisting of only one TDP each time.
6. The autozero/gain-switching stuff isnt yet included in this design, but will sit in front of the jfet-AFE like in the 3458A. I still need to design it.

The JFET-AFE could also be done as a differential input, but i dont know what parameters will be affected, since im not capable of fully designing a suitable differential cascoded AFE myself. Since the 3458A seems to do well with its AFE, i just copied it hoping for the best.
LEMOs + maybe thermal jumpers for even better thermal coupling are indeed a good choice and ill also go that way.

@ Kleinstein:
Indeed RN6 is probably the most problematic network with its several 10mW dissipation swings. I hope the thermal stabilization (like HPM7177) will help with it, but im unsure if were still talking about TC-effects or already power coefficients, which are of course not as easy to deal with.
Increasing the value as suggested should help, but i have to do calculations again how that influences parameters.
For people that dont use TEC based thermal stabilization of their AFE the trick from CERNs PBC might help: keep the network-temperature constant regardless of dissipation changes with a controlled heater thats thermally connected to it
2x VHD200 might also be an option as a last resort.

Need to read the thread again about the switch-discussions between Julian and you, to produce a nice AZ/Gain-switching in front of the JFET-AFE.

Attached is a prototype-picture of my first Rev. 0 HPM7177-variant. Yet without aluminium blocks and not completely working (hence the logic analyzer...).

http://cds.cern.ch/record/643294/files/cer-002399331.pdf CERN PBC-paper

[Kleinstein]

With RN6 the problem is with the power coefficient, so the input voltage changing the power and this way effecting the resistance ratio. Part of the effect can be local to the resistor and thus a heater and even if using 1 or 2 of the resistors in the network for this would not fully help. This is especially the case with the BMF resistors. With thin film resistors chances are a bit better that the power coefficient is close to temperature change times TC.  The balance with RN6 is between the power coefficient (causing INL) and resistor noise.  I have not tested the TDP resistors, but from my experience the MS ADCs the critical power level is about in the 5 mW range for networks in SO16/SO8.

The auto zero switching before the JFET amplifier can also be used in a kind of differential way. Many meters only do it pseudo differential (one side close to ground), but there is nothing to prevent switching between 2 really different signals. This way I get the 20 V range in my DMM circuit. However it gets a bit tricky with gain.

For the extra driver OP-amps in the 10 to 5 V stage it may be a good idea to use a lower supply voltage there, possibly down to the 0/5 V as for the ADC. The output should not go higher anyway and this would reduce the heating and ease limiting the output voltage. Chances are one would loose a little (like 10%) of the ADC range anyway due to clamping and limited drive.

[julian1]

For the power supplies, I have a salvaged 34401a/34970a transformer, also available for sale as replacement parts.
 
The tranformer's molex connectors/ and pinouts were copied for a test pcb, with some extra jumpers for the screen/guard part.
The 34401a transformer has an isolation screen but the service manual schematic shows it isolating the earth-referenced/ winding which is not useful.
Functionally, it works, but the primary/secondary has measured capacitance of 58pF which is not good for CM noise.

There are quite a few eevblog threads on low-noise dc/dc converters.
Designs include controlled-slew (lt1533), sin/triangle-wave, current-mode or open-loop push-pull.

https://www.eevblog.com/forum/metrology/(3300)-wavetek-7000-the-hidden-gemstone/25/
https://www.eevblog.com/forum/projects/lt1533-lt3045-low-noise-dcdc-pcb-suggestions-needed/
https://eevblog.com/forum/metrology/power-supply-for-voltage-references/
https://www.eevblog.com/forum/metrology/keythley-2612-teardown-and-repair/25/
https://www.eevblog.com/forum/metrology/dmm7510-coax-transformer/ 
https://www.eevblog.com/forum/projects/what-kind-of-transformer-is-this-(eevblog-1119)/
https://www.eevblog.com/forum/projects/low-common-mode-noise-dcdc-converters/


But I am wondering about a self-resonant push-pull approach, as outlined in the Jim Williams AN118, but adapted to low voltage.
Some quick experiments with a high-AL nanocrystalline core, show it's possible to create suitable windings with a measured Cps <= 1pF .

Is there a better approach?

[julian1]

For the amplifer -  the good ideas (non differential) are already given in this thread.
eg. HP/ 3458a for design inspiration, with (optional) Kleinstein modifications for improved linearity, and bandwidth across ranges.
I did some quick tests for linearily, but am not confident about control over confoundinig issues, so it needs to wait  (leakage due to guards at wrong potentials, emi on sig-gen for supply sweep, limit of DMM 100mV range).

Noting that the amplifier is not really in a low-noise configuration due to low cascode base current/ to reduce <strike>Miller</strike> Early effect. and with inductor repalcing low-value source resistors.
lsk389 is less noisy <=1uVpp/ 0.1-10Hz. than jfe2140.
jfe2140 5-6uVpp but seems to settle down 24hours after heat/solderiing to 1-2uV. but quite popcorny, not a guassian distribution.
if3602 is qualitatively different, but has a thermal walk - probably would need a per-cycle AG function/ with a DC source for low reference voltages.

these were quick tests mostly for function - not sure if they are in-line with expectation. It is evident that better shielding/supplies are needed, and I am quite capable of screwing something up.

[Kleinstein]

The main advantage of the resonant converter is that it can work well with loosely coupled transformers and more stray inductance, like with the 2 cores in series. The energy stored in the core is not lost or causing ringing.

For the number of turns one has to choose it according to the voltage / magnetization level, not only the inductance. The dirver circuit than has to work with the inductance one gets from the transformer, not so much the other way around.
It is not only about low capacitance, but also low effective voltage. Here it can help to start from a relatively low voltage, which is easier for a DIY transformer anyway with a relatively low number of turns. It can also help to just have a low voltage (e.g. 5 V) winding on the secondary and generate the higher voltages (like +-20 V) via charge pump / voltage doubling rectifier.

So far I have tried the SN6505  hard switching driver. However it has a weak point in using some spread spectrum mode with some 50 Hz FM modulation that may cause some LF noise. Otherwise it is OK-ish and like other higher frequency converters it needs care with the fitler layout as trace inductance can matter. The relatively high frequency allows for the use of MLCCs in the filter / charge pump which is nice.
A high frequency also meany the transformer can be small and thus naturally low capacitance.  TI calls it low noise, but I consider it low noise in the reasonable easy to meat EMI limits sense, not really low noise for a sensitive instrument. It may still work with an external clock to get rid of the spread spetrum part.
Another option I have tried is µC (output side) controlled old style BJTs to drive a relatively large ring core with high Al and quite some RC snubber to suppress ringing. It works, but is a bit clumbsy and the capacitance is not that small, though likely still OK.



For the JFET noise the relevant frequency depends on the speed of the AZ cycle that is used. With a 1 PLC mode this would be some 25 (30) Hz and with 10 PLC 2.5(3) Hz. So the 0.1 - 10 Hz band may be a bit misleading with too much weight on the very low frequencies.  From my experiance it seems to be normal to have popcorn type noise for the low frequency part of JFETs. The steps just can be quite small with larger JFETs.
From the data-sheet values the JFE2140 should also be relatively low noise (0.12 µV_pp with 2 mA - likely for 1 FET and thus some 1.4 times that in differential mode).  With a low 200 µA the expected noise is about 3 times that, but there can be scattering between parts.

[Echo88]

Question:
Im getting very nice and linear results with my prototype HPM7177-version between about +-7V. More than that (i can measure up to +-11.5V) and its getting very nonlinear, with errors approaching several 10mV.

An applied input voltage of say 10V is measurable after both OPA189 without voltage errors (so the ADGs and OPA189 arent the issue) and the voltage at the ADC input cap is about +5.0018V and +0.6mV to gnd.
The 5Vref in my variant has about 5.357V due to usage of TDP1603 instead of PRND and the resulting slightly different divider factor.
The ADC AVDD is 6V to account for the 5.357Vref, which is within datasheet spec.
Since the common mode voltage for the input difference stage is derived from the internal 2.5V ADC-ref, might this be the cause for my nonlinearity-problem above +-7V?
Since the TDP1603 are 10k in the difference stage i doubt its them misbehaving due to TC/PC.
I could derive Vcm also with a 1:1 divider from the 5.357Vref (->2.6785V), but that would necessitate another OPA189 + divider...or a 1:4 divider directly at the 10Vref.

Edit: Nope, modified the prototype and that wasnt it, as expected. Now what could be the cause...

[Kleinstein]

Finding the cause for relatively small INL effcts is tricky. 10 mV out of 10 V are however no longer a small effect. So I would exclude a thermal effect in the TDP resistors and also the OP-amps, unless there is something really wrong.  I may help to know in which way the nonlinearity happens, so a curve of the INL over voltage.
Another point is having an accurate schematics.

In the plan shown the voltage clamping parts may be an issue - not sure what they are and if installed at all.

[dietert1]

When i look at the AD7177 datasheet there is a maximum voltage rating of 6.5 V but in the text after "GETTING STARTED" they call 5.5 V the maximum supply voltage. Shouldn't be difficult  to reduce the 6V to 5.5 V for a test.

Typical 6.5 grade or better meters i tested all exhibited temperature coefficients between 1 and 0.1 ppm/K. Numerical compensation using a temperature sensor inside the meter works yet is always hampered by the different dynamics of the sensor. The HPM7177 with it's oven is a good example showing what to do: A ppm or sub-ppm meter should run inside an oven or a chamber. The power supply should be outside of the oven. Using a chamber requires a constant (synthetic) mains supply.
I am also trying to work out an accurate meter to run inside an oven. As Kleinstein wrote in his DIY multi-slope ADC thread: Using conventional circuitry at higher voltages one can beat those integrated converters. My own build inherits from the Prema 6048 meter. With about 2 W of heat output it needs a peltier oven (FPGA, 2x LTZ, LTC2386).

Regards, Dieter

[Echo88]

Changed the 6V rail to 5.5V as suggested, changed Vcm to Vref/2 = 2.679V and reduced the internal gain.
After trying to get it to work the whole day with several tests, measurements of the input stage and software modifications i now got it to work within +-10.7Vinmax with <=4ppm INL, without temp control, shielding and long wires between the used F5440B calibrator and the prototype. Good enough for now and +-10.7Vinmax (Limit: 5.358Vref *2 = 10.716V) are not quite 12V, but still enough overrange i think.
When the milled aluminium block arrives i can continue with the TEC control and add shielding to get more stable results. 
Schematic is attached in reply 157.

[dietert1]

Did you remove R18 .. R20 in the frontend? Is THJP some kind of transil?

Regards, Dieter

[Echo88]

Sorry referenced schematic was from my HPM7177 variant in reply 157.
The high impedance frontend idea isnt yet realized. Yeah R18...20 wouldnt be populated in the real implementation. THJP are thermal jumpers, i dont know of any symbol that would fit its function as a thermal bridge.

[Echo88]

I know i already asked the question already once in another thread, but i reworked the schematic suggestion for it:

As im preparing the revision 2 of my ADC-board with less bugs, the Vcm change and general optimizations im still unsure about the correct way to properly average the Gnd-sense of a quad LTZ/ADR1000-array.
Since the original HPM7177 is limited in noise by its single LTZ1000 i included the quad LTZ/ADR to be able to achieve the lowest noise possible as an option.
In my opinion each LTZ is coupled relatively hard to ground via their respective 0,1R resistors, with their respective reference current (about 5mA or so) + shared refdivider-current (5.8mA from 7Vref->5Vref divider + 5.4mA from 5Vref to 10Vref amplifier = 11.2mA max /4 -> 2.8mA per 0.1R resistor added).
Due to this hard ground coupling and the temperature stabilization of the pcb itself the references should be very stable and therefore their currents. This should prevent feedback or instability issues, so i guess the gnd-sense buffer OP can be omitted and all Gnd-sense-pins can be connected together without issue?

At roughly 500€ for a populated quad LTZ/ADR1000-array the circuit necessitates careful thinking. 

I attached the schematic of the proposed quad array, with both gnd-sense variants: averaged and buffered via OP U33 + RN11 or hard connected together.

[Kleinstein]

For the ground side one should be able to directly couple the ground sense and use current compensation for the ground drive side. So the ground drive would not be directly connected to ground be provide about the right current for each reference and than have the GND link with ground sense. So one could skip the extra buffer at the ground side.

One could also use the averaging resistors also to add some filter action - so have space for a film capacitor (e.g. 5-10 µF range) to ground.

The 7 to 5 V divider looks rather low in resistance - this would make the trace resistance rather critical and adds quite some load to U32.

Ideally one would also like to have the option to have access to the individual 7 V references, e.g. so see if one of them is drifting or showing popcorn noise.
I don't see a real need for the 10 V reference level. The 2.5 V Vcm could be obtained directly from the 5 V level or the same divider as the 7 V to 5 V.

For the start I would consider the quad reference overkill. The would be a part to populate only if everything else works. Even than 2 x ref. is likely good enough, especially if the ADR1000 is used. The main point should not be just lower noise, but a way to check for samples with excessive drift.

[dietert1]

In my design i have two LTZ1000 in series to implement a 14 V reference. I hope to avoid Gnd sense and current compensation by having a second ground plane AGnd that only takes the zener current of the lower reference and two constant current loads of the reference. Except some opamp inputs connected to AGnd all other (variable) currents get routed to the supplies, for example the heater currents. Near the LTC2386 ADC where AGnd becomes digital Gnd i have a 10 Ohm resistor. It should measure 50 mV in the end and if necessary it can become a short.
It should be useful to start with 10 Ohm instead 0.1 Ohm resistors and think about what happens. Maybe you want to change the four Gnd connections of the LTZ oven control.

Regards, Dieter

[Echo88]

Completely overlooked the possibility to use the 2.5V tap from the 7->5V divider, good find
Together with increasing RN5 to the 10k variant that decreases the gnd sense current greatly.
Since the whole board is temp stabilized and the references are not varying im unsure wether a gnd current compensation makes sense here, especially now that the gnd sense current is way smaller, thats why its not implemented yet.
Could totally understand it in a frontend with varying input voltage and therefore current into gnd through a range-divider though, like done in the 3458A were it would otherwise shift gnd.
Filter cap and access to each reference was added, thats certainly useful, especially for popcorn noise detection.
I thought the 10Vref was used for gain stability verification/calibration with the switches and therefore makes sense?
The quad refarray is indeed overkill, but since i have enough LTZs for it and wants to see just how low noise i can go with an ADC i want to try it here. I have two ADR1000, but they arent available right now normally and im cautious to trust them.
Drift intercomparison between the references can certainly be done, but only with more switches and im not yet implementing it in this revision, pcb space is already becoming scarce. 

Still need to do a noise simulation to see where that gets me, the shown values on the schematic are just for comparison.
The averaging network RN10 might produce drift issues when not all included resistors drift/age the same, might need a higher quality network than standard 4x1206 SMD-array?

Separate gnds to the respective ref-heaters makes sense, it avoids the substantial ~240mA through the gnd-planes, nearly forgot about that, thanks.
That will also require a supply redesign with beefier LDOs and better coupling to the cooler...always more work to do.

Schematic with changes is again attached.

[Kleinstein]

The resistors for reference averaging are not that critical. They only effect the difference between the reference - so something like 1-2% of the full reference. So standard SMD arrays (e.g. ACAS, MORN) can be good enough for this. No need to go really fancy here. The power loss is also rahter small and not much excess noise with only a small voltage.

The ground current compensation is from a fixed negative voltage to reduce the current flowing towards the central ground point. This also helps if the currents are constant, but with changes in trace restance and maybe connectors in the path if the reference are on there own small PCB.

The ADC (with dividers) gain check would ideally use the 7 V ref signal directly. An amplified 10 V signal would add an extral level of uncertainty with only minimal less noise. A 10 V level may be useful for ACAL with an external high voltage divider though - but no super stable voltage needed here. Another point may be a comparison with an external reference.

The reference schematics look a bit different from the standard circuit - may be the cern version. The use of dual supply OP-amps may be a bit tricky on start up and may need care with the power up sequence. I don't see an advantage compared to the standard circuit using LT1013.

[julian1]

Ignoring CM noise for a minute, I have a question about switcher ripple, because the potential for interaction with op-amp and amplifier PSRR is something I don't understand.

If a 100Hz mains transformer is swapped for a mains transformer + 10kHz low-noise dc-dc switcher, then a typical op-amp (eg. opa140) loses 40dB of its supply rejection function. eg. 100dB to 60dB eg. 100x PSRR.
A 7800 regulator is already fairly good (versus some LDOs) - offering 70dB ripple-rejection out to 10kHz.
Is there a way to think about the combination of op-amps and regulation, to identify the max ripple on the supplies (and therefore required post-regulation) - if the DMM needs >= 140dB for measurement?
Ripple is somewhat sinusoidal/symmetrical for push/pull, but I don't think it makes sense to assume linear/cancelling contribution in the case of supply rejection (consider also AZ frequency and line-synchronization and harmonics).

3458a already has cap-multipliers with 78L/7900 right down at the AC line frequency ( RC=200R/15u=53Hz ) even though it uses a mains-transformer, and there are no dc-dc switchers creating high-frequency ripple.
Although AC measurement ranges would be expected to be more sensitive than DCV, with better AC supply rejection needed.

A resistor is low capacitance, so using RC or a RC based capacitor-multipler is always possible after the dc-dc switcher, and before the linear regulator.

[julian1]

The size of electrolytic caps surrounding the coax transformer of the DMM7510, suggests the operating frequency may even dip down into the auditory range.

Edit,

On another note - just using a mains freq transformer, may yet work, holding the advantage of being a simple and proven design.
The difficulty is coming up with a feasible and practical construction. Here one could use the same trick, placing the primary-secondary windings at opposite ends of a toroid, and using copper tape - as a sleeve and for screen/guard.

I tried with 300 turns on a high-AL NC toroid, trying to roughly match the spec of a similarly sized laminated iron toroid.
With 15H, it's ok at low-voltage, but saturates with 250VAC. So at a minimum it could work as part of a two transformer solution.

[Ole]

Does anyone know the current draw on the 3458s + and - 18V Rails during normal operation?

[Kleinstein]

If the layout is correct and not ground loops / bad ground point the ripple rejection of the regulator and amplifiers just mulitply or add as dB values. However there is a chance to have a not so ideal layout. Another point is that capacitor ESR may contribute to the ripple - so the rejection for the regulators can depend on the details.  With relatively low power one can use relatively large capacitors to start with and also possible added LC filtering for a higher frequency version. Especially push pull stages may not run with a sine, more like a square wave and possibly less ripple.

The simple pre-stabilization (cap mulitplier) can be an option, though it looses some 0.5-1 V.

With a toroidial transformer and windings only on opposing ends this may increase the magnetic stray field of the transformer. It is a balance between capacitive coupling and magnetic coupling.
For low coupling transformers there is also the version with a normal primary all around the core and then the secondary with maximum distance through the center of the core, either one side or as a figure 8.
This way at least the magnetizing current does not produce an extra stray field and the core usually is conductive anyway.