@branadic
Have you already posted about the ADR1399 PWM DAC somewhere? I would love to learn more about it. I've recently been playing around simulating something similar using a passive 3 pole RC filter (3 stages of 10K/100nF C0G) which does indeed reduce ripple, but assuming I want 1uV settability, I would need a 23-bit resolution PWM signal. While that is possible, it pushes the PWM frequency very low, and I'm not sure how to make a practical implementation. Perhaps reduce settable resolution to 10uV?
@gamalot: Someone I know also just got an ADR1399, the printing was similarly crusty but the package looked to be in better shape.