ADR1001 - Ovenized Voltage Reference System

[iMo]

I put 100k directly at the 10V_out and 10V_gnd star posts at the board and then the 1m lead wires go to the 34401A set to >10G.
The delta I see is ~170uV with 16V power and 100k resistor.
There is the 1uF||4n7 at the buffer's output so I doubt the input of the dmm could upset it more.
It looks to me like they wired 1.7ohm to the buffer's output.

It is a prepro sample (1001XEZ), none DS, all info we have is in this thread..

[magic]

Yes, I know you measured it differently. It was a suggestion, not a question

There is the 1uF||4n7 at the buffer's output so I doubt the input of the dmm could upset it more.

Are these values recommended by Analog or something that just happened to be in your junk box? Why are they there?

It looks to me like they wired 1.7ohm to the buffer's output.

That's one possibility.
But why would they do it?

[iMo]

There is the schematics of the evaluation kit available (also in this thread) I took as the base.
The kit has been pre-released and some people here have it (the same chip batch I have).
There is the spice model as well with the test jig.
They use 1uF mlcc ceramics there, after a discussion here I opted for aluminum as it has a higher internal resistance.
The 4n7 is there to suppress higher frequencies coming from leads (there is a ferrite bead/cmchoke w/ 3turns on the leads too).

[mawyatt]

...
How would you wire the npn inside the loop with the 1001?

You would need to break the loop somehow, likely not easily within the 1001. Seems ADI already did this with the 1002, which seems like a good idea to include an EF even if the lower output Z isn't required.

Best,

[magic]

Well, if there is internal 1.7Ω resistance, it's not modelled in SPICE
And it's unclear how the value would increase to 2Ω on 12V supply.

OTOH, the model does predict instability with more than 10Ω output ESR.

[mawyatt]

Well, if there is internal 1.7Ω resistance, it's not modelled in SPICE
And it's unclear how the value would increase to 2Ω on 12V supply.

OTOH, the model does predict instability with more than 10Ω output ESR.

That's not showing instability, but the output "Z" as it's driven by a current source of 10ma delta I, which produces a voltage response of delta V. This equates to dynamic output Z of delta V/delta I.

Most op amps don't go unstable with large or larger ESR values hanging off the outputs, they go unstable with smaller ESR, assuming a sufficient shunt capacitance to create enough phase shift with the dynamic output Z to cause the phase margin to degrade.

To check for instability one could inject a current step at the output and look to the response and settling of the output voltage change.

Best

[magic]

Yes, that was the point. The model shows very low output impedance, less than 1mΩ, surely not more than 1Ω.
Every decent buffered voltage reference has load regulation specs in single digit ppm per mA.

Instability was a separate sim, which anyone curious may easily produce himself.


Regarding stability, most opamps are also stable without 1µF output capacitance, so this is not exactly a usual opamp.

I don't have my hands on this chip so I won't tell you how it works, but the model operates down to ridiculously low input voltage like 10.1V. If the model is right and this is really an LDO, maybe a maximum limit on ESR doesn't look so exotic anymore.

[Kleinstein]

Compared to the simulation the real world chip could have some resistance from the "pin" , maybe bond wire (internally there could be two - so AD would have a way around much of it). So a little output restance would be normal, but 1-2 Ohm sounds too much.

An unnoticed, relatively small residual amplitude oscillation could cause all kind of strange effects. The output capacitance (too much ESR) could be an isssue.
If unstable, chances are that also just extra capacitance at the output could change the voltage.

[iMo]

...
How would you wire the npn inside the loop with the 1001?

You would need to break the loop somehow, likely not easily within the 1001. Seems ADI already did this with the 1002, which seems like a good idea to include an EF even if the lower output Z isn't required.

The 1002 does not exist, afaik, that "1002" above is my suggestion to ADI for the upcoming 1002 (if any).. 
I would wire the output buffer's input directly to the first divider, with only 1 pin for the external capacitor, that is how they can get 1 pin free and that pin could be routed to INV0 (in my above 1002 schematics).

[sahko123]

The opamp is wired to make it as configurable as possible to either act as an inverter to get -5V or a double to act as 10V output or even to just buffer the output. Having the feedback network internally i think is better for stability.

Its also not guaranteed to be used with Vdout specifically hence the external input connection

[Kleinstein]

The internal resistor network is nice. However the direct connection to the op-amps output is a problem as this makes the amplifier sensitive to loading.
In the current configuration it is only usefull with rather low load on the OP-amps output (e.g. more than some 100 K). Still the resistance should not be more than 1 ohm - more like 0.1 ohm.

[mawyatt]

...
How would you wire the npn inside the loop with the 1001?

You would need to break the loop somehow, likely not easily within the 1001. Seems ADI already did this with the 1002, which seems like a good idea to include an EF even if the lower output Z isn't required.

The 1002 does not exist, afaik, that "1002" above is my suggestion to ADI for the upcoming 1002 (if any).. 
I would wire the output buffer's input directly to the first divider, with only 1 pin for the external capacitor, that is how they can get 1 pin free and that pin could be routed to INV0 (in my above 1002 schematics).

Agree, this is one way ADI could have created the I/O pinouts. Since this is apparently an early rendition of what they will offer, and don't "see" any advantage to what they've done pin-out-wise, maybe they are "listening" and will follow your "suggestion"

Best,

[iMo]

Replaced the 1uF alu with 1u5/25V tantalum one. Vin 15V.
dmm       10.000.016
w/ 100k    9.999.850V
166uV diff

Hmm, it seems I have to go back to my previous schematics with an opamp and some transistors, in order to be able to drive 10k load 

@magic: where your ltspice model comes from?

[dietert1]

You could repeat this test with 200K and 50K resistors to see what happens. To me the observed behavior appears strange, as the voltage divider 0.5 already represents a load of 20K. These things sometimes happen if you put a load to a previously unloaded opamp or when the opamp output current changes direction. Or the force/sense scheme you are missing limits the amplifier performance. Or there may be oscillation and the connections you make are antennas. Anyway, without datasheet it's guesswork.

Regards, Dieter

[iMo]

@dietert1 - I will do tomorrow, sure. I did today with 10k and 1k but the voltages dropped too much for my taste so I did not mess with it for too long.
Btw. - switching dmm input from >10G to 10Meg changes the reading by aprox 4-5uV (but that is a different story as the lead wires are long).

[magic]

The opamp is wired to make it as configurable as possible to either act as an inverter to get -5V or a double to act as 10V output or even to just buffer the output.

Not holding my breath for negative output if parts of the reference structure are tied to the substrate like in ADR1000.
There will likely be absolute maximum rating: BUF_GND = REF_GND ± small delta.

Replaced the 1uF alu with 1u5/25V tantalum one. Vin 15V.
dmm       10.000.016
w/ 100k    9.999.850V
166uV diff

I would definitely check with a scope because it's an utter waste of time to debug an unstable circuit.
Then, measure voltages on all relevant pins and see if it really is the amp or something else that changes. And what happens at the inputs of the amp. If BUF_S is rock stable then yeah, wtf.

I agree that less than 1mΩ is perhaps too optimistic (and even if it's real, you won't see it without measuring on the pins directly), but more than 1Ω seems a bit much. What's the resistance of your wires, by the way? I think even that is still less than 1Ω.

@magic: where your ltspice model comes from?

I just installed the latest LTspice, ver 17.0.36, 32-bit.

BTW, I think this model may be transplantable to older releases. I was able to include it even in LTspice IV, but I haven't put the files in the library yet and I don't know how to include a symbol from the working directory, so I couldn't put it on the schematic and see if it works. Sorted it, outcome: "Fatal Error: Singular matrix:  check node u1:isense_m"

edit
I see that the current version on the website is 17.0.35 and I'm pretty sure that this is what I downloaded before.
Nevertheless, help → about says that I'm on 17.0.36.

Can't explain this. Have fun

[sahko123]

The opamp is designed to be able to give a negative output voltage

[iMo]

@magic: yep, the 17.0.36.0 dated Dec13 2022 has got the model finally (win64 version), I downloaded just now.
My wires are made of copper, sure, no more than 17mOhm per wire on my board.. 
But shit happens..

PS: I've a look at the pins with my oscope (analog 80MHz) and I do not see any oscillation at the output with load or without load (or it is below 1-2mV).

[magic]

The opamp is designed to be able to give a negative output voltage

No NPN collector nor PNP base on the same die as the LTZ/ADR1000 reference structure can go lower than zener anode.
Every such element is the N of a diode whose P is the anode, with predictable consequences.

So I see a few possibilities:
1. ADR1001 will stop working sensibly if you apply negative voltage to BUF_GND.
2. ADR1001 somehow uses a different reference structure, maybe on a different process (dielectric isolation?).
3. The amplifier is a separate die (feedback resistors may still be ovenized on the main die, they are likely dielectrically isolated anyway).
4. They somehow designed an amplifier which outputs negative voltage without using NPN collectors or PNP bases below ground.

Off the top of my hand, I'm not sure how the output stage of 4 could work and 2 or 3 would drive cost up.
Given the naming of the BUF_GND pin, my initial bet was on 1, but maybe you know something

edit
OTOH, the buffer's feedback network pins are called INV. Maybe you guys are right.

Actually, this device could simply be a standard ADR1000 application built in hybrid technology, consisting of modified ADR1000 plus a few opamps, maybe even a MLCC or two.

[iMo]

In the ADI's EZone there is a Q/A on the heater opamp HTR_GND pin with the answer it can go negative up to -15V (together with the HTR_ILIM pin).

[iMo]

@dietert1: below the V_out vs I_load I get today..

[magic]

In the ADI's EZone there is a Q/A on the heater opamp HTR_GND pin with the answer it can go negative up to -15V (together with the HTR_ILIM pin).

Note that the positive supply of the heater opamp is taken internally from REF6P6S. Quiescent current variation due to changing negative supply voltage or base current variation of the heater NPN may cause loading errors there. That's what the simplified schematic suggests, at any rate.

BTW, your schematic shows VDIN connection to REF6P6F, but I suspect that you used REF6P6S, which is the better option of course.

@dietert1: below the V_out vs I_load I get today..

This looks like a resistor, but didn't you say that the slope was different on 12V supply?
Monitoring BUF_S could tell if the internal output of the scaling amp stays constant or if it drops under load too.
Monitoring BUF_INP could tell if the input to the amp is constant.

[iMo]

The 6V6F, 6V6S, VDIN are pins 4,5,6 and are wired together in my wiring.
That 12V slope was "aprox". Take the 1.7 as the slope. I stopped measurements at 12V at this stage as it is too close to 11.3V where the stuff starts to show values.
There are 2 REF_GNDs on the package in reality (14 and 15), I have two separate wires connecting them to the 10V_GND star.
PS: I measured the voltages around the ref_opamp and buff_opamp with a 47k load on/off, I do not see a relevant change except the measurement noise.
PPS: long time back I draw a schematics for mike_mike called "power_supply_shorter" he was using extensively afterwards. Perhaps a high time to try with it here.. 

[sahko123]

The datasheet does actually state that the network can be used with the internal opamp to create negative output voltages.

[iMo]

Ok, after a good lunch my current understanding is as follows:
1. there is an 1.7ohm resistor wired after the divider
2. with the 10V the resistor applies as the buffer's feedback BUF_S goes to the output divider, so the resistor works as "the bond wire"
3. with 5V the resistor does not apply as the buffer's feedback goes to the output pin, after the resistor (the resistor is within the loop)
4. they put the resistor there to mitigate instability with 1uF MLCC output capacitor
5. the buffer itself works, as I do not see a change in the feedback path when loading its output (at 10V setup)..
 
PS: hopefully my adr1002 will arrive soon