Clearance between conductors in primary side of offline SMPS?

[Faringdon]

Hi,
We all know on top layer, clearance for L and N should be 2.5mm. (no con. coat, IP67 sealed enclosure)
However, once  you are downstream of the input fuse, the 2.5mm clearance is "relaxed"
(At least this is what you actually see in offline SMPS when you tear them down)

What is the actual standards clearance value when you are downstream of the input fuse?

Also, as you know, upstream of the mains FWB, capacitors must be X2 rated...downstream of it, and they dont need to be.
No regulation actually states that the FWB is the defining line , but it is the "accepted norm".

Has the new standards gotten round to this yet?



Also We all know the following in page 9 is  good summary of current clearance standards.
https://www.alternatezone.com/electronics/files/PCBDesignTutorialRevA.pdf

But as we know, TO220 legs D and S in Flyback are often >800V and separated by <1mm

As you can see, for a TO220 FET, the through_hole of the pad needs to be 1.2mm in diameter, the “annulus ring” of copper of the pad needs to be at least 0.3mm thick. This means that there is a maximum of 0.74mm of clearance between Drain and Source PCB copper, and the flyback has a peak Vds of 600V.
TO220 FET datasheet....
https://www.st.com/web/en/resource/technical/document/datasheet/DM00049184.pdf

Zillions of offline SMPS have only 0.7mm clearance between D and S.

[T3sl4co1l]

Transient limits define this. Functional spacing for known voltage is very small indeed (0.5mm?).  FWB will break down above a kV or so.  MOV probably a bit less.  Input cap + FWB can be less still (500-600V at Vin max + surge peak), but needs a beefy enough cap.

Tim

[floobydust]

Hi,
We all know on top layer, clearance for L and N should be 2.5mm. (no con. coat, IP67 sealed enclosure)
However, once  you are downstream of the input fuse, the 2.5mm clearance is "relaxed"
(At least this is what you actually see in offline SMPS when you tear them down)

What is the actual standards clearance value when you are downstream of the input fuse?

Also, as you know, upstream of the mains FWB, capacitors must be X2 rated...downstream of it, and they dont need to be.
No regulation actually states that the FWB is the defining line , but it is the "accepted norm".

Has the new standards gotten round to this yet?



Also We all know the following in page 9 is  good summary of current clearance standards.
https://www.alternatezone.com/electronics/files/PCBDesignTutorialRevA.pdf

But as we know, TO220 legs D and S in Flyback are often >800V and separated by <1mm

As you can see, for a TO220 FET, the through_hole of the pad needs to be 1.2mm in diameter, the “annulus ring” of copper of the pad needs to be at least 0.3mm thick. This means that there is a maximum of 0.74mm of clearance between Drain and Source PCB copper, and the flyback has a peak Vds of 600V.
TO220 FET datasheet....
https://www.st.com/web/en/resource/technical/document/datasheet/DM00049184.pdf

Zillions of offline SMPS have only 0.7mm clearance between D and S.

You have already visited this question as treez/ocset/cupoftea/flyback etc: https://www.eevblog.com/forum/eda/pcb-spacing-of-to220-fet-legs-in-offline-flyback-smps-pcb/
"As you know, it is illegal to have an offline 230VAC flyback SMPS which uses a TO220 FET in the PCB without legs bent to get the clearance above 1.5mm from drain to source." [...]

Did you figure this out, an answer why? There are two reasons the spacing requirement could not be met.
P.S. I suggested you make your products bigger, you know an 0805 across mains does not turn out well.

[Faringdon]

Thanks, the 0805, 4n7,  X7R , 1kV capacitor is across the rectified DC bus...(which can 'normally' go up to some 373vPK) ..and is in parallel with two 400V rated electrolytics....if the bus goes above 1kV....then the electrolytics have had it anyway.
As you know, the 1mm clearance will be fine, and wont flash over.......flash over voltage would be well in  excess of 3kV for this 0805.

[Niklas]

Note that there are both clearance and creepage rules that applies. Define the pollution degree and overvoltage category for you application and look into the tables in the standard.

Does the voltage between L and N change significantly if you compare both ends of the fuse? We assume that the fuse is not burnt. Both clearance and creepage distances refer to voltages, so why should there be any difference in the requirements before and after the fuse if the voltages are equal?

373V DC => Use 400V. Assume pollution degree II and PCB material, then the required creepage distance is 2 mm. It is doable with 0805s, but not with a 0805... The voltage rating of the part is not relevant as the limitation is in the footprint on the PCB.

[floobydust]

Thanks, the 0805, 4n7,  X7R , 1kV capacitor is across the rectified DC bus...(which can 'normally' go up to some 373vPK) ..and is in parallel with two 400V rated electrolytics....if the bus goes above 1kV....then the electrolytics have had it anyway.
As you know, the 1mm clearance will be fine, and wont flash over.......flash over voltage would be well in  excess of 3kV for this 0805.

Uh no, the 3kV/mm creepage number comes from another safety standard and depends on altitude, electrode geometry, humidity, pollution, material, ozone build up.
For long-term stress I would follow the safety standard 400V PDII FR-4 2mm as a minimum. You need to consider if it arcs, what is the fire protection?
Recent SMPS-related recall it has a 12A fuse which of course allowed plenty of smoke despite a naive designer thinking it will be fine.

How strange your designs are or maybe the "boss" or "customer" is the one to not give one extra mm. Such a small world.