Hehe, I have my excuses for being lazy, the sound good to me at least!
It's not a deal breaker, but I think that is one useful feature that CvPCB has over the EESCHEMA assignment tool, shame they can't add it to V5, perhaps for RC3? Are there any KiCad dev's in here who can say if this is a warranted suggestion or just me being fussy?
Thanks for looking btw!