Anyone care to take a once over my first design in KiCad?

[thomasb9511]

Hey all,

I've been getting back into the hobby after a few years of..... stuff, and I started to pickup KiCad as I now use Linux as my main OS.

Attached is a simple breakout for the SN74HC00N quad NAND gate IC.

Would some be able to see if I made any mistakes?

[spudboy488]

Add a bypass cap (0.1uf or so) on U1.14 to ground.

Why so many ground vias? You have 7 connector/dip vias already.

The bend in the QA trace is possibly too close to the bend in the B1 trace. I like to even out the spacing when makeing runs like that.

[thomasb9511]

Add a bypass cap (0.1uf or so) on U1.14 to ground.

Why so many ground vias? You have 7 connector/dip vias already.

The bend in the QA trace is possibly too close to the bend in the B1 trace. I like to even out the spacing when makeing runs like that.

Thanks,

C1 is my bypass cap.

An old friend told me a long time ago that its a good idea to strongly connect your ground in cases like this. Does stitching like this negatively affect things?

Once I can, I'll even out the spacing. Is it possible 20 mil traces are a bit too big for this?

[spudboy488]

Thanks,

C1 is my bypass cap.

An old friend told me a long time ago that its a good idea to strongly connect your ground in cases like this. Does stitching like this negatively affect things?

Once I can, I'll even out the spacing. Is it possible 20 mil traces are a bit too big for this?

I didn't notice C1 on the schematic. The symbols are kinda of wonky on my screen for some reason.



I don't think the extra ground vias will hurt, it just seemed odd for a (probably) low frequency board.

I prefer 8-12 mils for signal and 20 mils for power, but that's me. Others who are more in the know will be able to guide you better.

[Doctorandus_P]

As you already have a continuous GND plane, and with zone settings that let the GND plane sneak in between the 0.1" header pins there is no need for a any of the via's, nor for the GND plan on your "Front" layer. But it does not hurt your design either.

A very slight improvement may be to use the "Front" layer for a +5V plane, which will form a distributed capacitor with your GND plane. But such thins only become usefull at much higher frequencies (HC TTL is an old an "slow" technology.)

spudboy488 is seeing the square question mark symbols because the project-cache.lib is missing from the zip file. This library contains cached versions of all schematic symbols, and it is an important file you should always put in your backup / archive of a project.

On my system I can see the schematic normally, but that is because I have the same library setup as OP. spudboy488 apparently has another library setup, and when KiCad can not get the schematic symbol from any library it shows the question mark symbols.

This is expected to change in KiCad V6, where copies of the library symbols will be embedded in the schematic file itself in the same way as footprint copies are now saved in the PCB file.

[poeschlr]

and when KiCad can not get the schematic symbol from any library it shows the question mark symbols.

Any library here includes the cache library which should always be shared together with the project.
- https://forum.kicad.info/t/what-are-the-cache-and-rescue-libs-and-how-does-the-schematic-rescue-dialog-work-kicad-version-5-x-and-earlier/21150
- https://forum.kicad.info/t/project-and-libary-setup-for-sharing-and-collaboration/20842