New stuff on the bench:
No, no new TEA but some experiments in time-nuttery:
It's a circuit that takes two 10MHz inputs and multiplies their frequency by 10 (using a 100MHz VCXO and an ADF4001 PLL chip).
One of the PLLs can be offset by a small amout (up to 1kHz ballpark) by mixing a I/Q IF signal (said frequency offset) into the PLL feedback. It's on the right hand side of the board, with the 1kHz I/Q signal fed into the mixers. The white boxes are 90° phase shifters operating at 100MHz, say one input @100MHz and two outputs by 90° at the same frequency. Two small mixers add or subtract the IF from the 100MHz. Their output is fed into the PLL chip. This causes the VCXO to tune at said frequency offset.
The other PLL is just a x10 multiplier.
Both PLL outputs are fed into another I/Q mixer, this one revealing the beat frequency of the two 100MHz VCXOs at its IF output. By measuring this IF frequency, one can detect small differences between the 10MHz reference inputs. At least this is the plan ...
Some more stuff to do, at this point it's just a proof of concept the PLLs and I/Q mixers are working as expected.