I received a sixth and seventh 16717A board today. I plugged what we'll call Board F into the mainframe as the only board installed, and immediately received an error upon bootup that said that the module failed its' high-speed system clock test, and it claimed that the frame may need service.
However, the board passes all tests with x modtests from within pv.
I then re-ran all tests by setting d=9 (but not r=9).
As it ran the test, once it reached the vramCellTest, it flooded the screen with information, mostly clock numbers and hexadecimal codes which I'm guessing relate to specific VRAM cells, the data sent and the data read back. It sat there counting down clock codes from over 2,000,000 for a good solid 30 minutes before it moved on to the next test. After letting it run, all the tests passed on debug level 9.
I pulled Board F out, and replaced it with Board G. The frame powered up and got to the Workspace system without throwing any errors, so I logged into it via telnet and then ran a suite of module tests through pv.
Sure enough, it fails three tests: cmpTest, calTest, and zoomAcqTest.
This one fails cmpTest in an unusual way, however:
Check POD1 Thresholds:
Slot E, Chip 9: . ........ ........ . ........ ........ Cal Clk No Act.
Slot E, Chip 8: . ........ ........ . ........ ........ Cal Clk No Act.
Slot E, Chip 9: . ........ ........ . ........ ........ Cal Clk Levels
Slot E, Chip 8: . ........ ........ . ........ ........ Cal Clk Levels
Slot E, Chip 9: . ........ ........ B BBBBBBBB BBBBBBBB Cal Clk Activity
Slot E, Chip 8: . ........ ........ . ........ ........ Cal Clk Activity
Check POD2 Thresholds:
Slot E, Chip 9: . ........ ........ . ........ ........ Cal Clk No Act.
Slot E, Chip 8: . ........ ........ . ........ ........ Cal Clk No Act.
Slot E, Chip 9: . ........ ........ . ........ ........ Cal Clk Levels
Slot E, Chip 8: . ........ ........ . ........ ........ Cal Clk Levels
Slot E, Chip 9: B BBBBBBBB BBBBBBBB . ........ ........ Cal Clk Activity
Slot E, Chip 8: . ........ ........ . ........ ........ Cal Clk Activity
Check POD3 Thresholds:
Slot E, Chip 9: . ........ ........ . ........ ........ Cal Clk No Act.
Slot E, Chip 8: . ........ ........ . ........ ........ Cal Clk No Act.
Slot E, Chip 9: . ........ ........ . ........ ........ Cal Clk Levels
Slot E, Chip 8: . ........ ........ . ........ ........ Cal Clk Levels
Slot E, Chip 9: . ........ ........ . ........ ........ Cal Clk Activity
Slot E, Chip 8: . ........ ........ B BBBBBBBB BBBBBBBB Cal Clk Activity
Check POD4 Thresholds:
Slot E, Chip 9: . ........ ........ . ........ ........ Cal Clk No Act.
Slot E, Chip 8: . ........ ........ . ........ ........ Cal Clk No Act.
Slot E, Chip 9: . ........ ........ . ........ ........ Cal Clk Levels
Slot E, Chip 8: . ........ ........ . ........ ........ Cal Clk Levels
Slot E, Chip 9: . ........ ........ . ........ ........ Cal Clk Activity
Slot E, Chip 8: B BBBBBBBB BBBBBBBB . ........ ........ Cal Clk Activity
> Slot E: Comparator Test Failed!
I'm about ready to give up on this boat anchor. This is potentially only one out of seven boards I've received that has successfully passed all of its tests, and even then, the mainframe doesn't fully like Board F since it throws a boot-time error about the system high-speed clock.