It looks (least for me) like primary trigger (or least counter trigger) is generated from one ADC 1GSa/s data also when there is 2GSa/s in use.
ADC is something like this Because can not know exactly in what mode they run this chip it is bit difficult to make some special test what can suspect. Perhaps system is designed for 1GSa trig and not even tried generate trig from 2GSa/s data stream. If it is designed for 2GSa/s trig then there is perhaps some bug how they pick up data from ADC for produce primary trig flag.
In all images signal to CH4 is 375MHz good quality sinewave from HP8644B (Agilent)
Trigger normal, edge, rising, DC
2GSa/s, vectors, Sinc OFF. Trigger level as high as possible for correct and stabile freq counter.
Here 57mV
Changed only trigger level bit higher to 58mV and noted that freq counter start drop out.
Changed trig level back to 57mV and changed Sinc ON. Frequency counter stabile and right.
Changed trigger level bit up, to 58mV and noted that freqquency counter start drop.
After this point I want drop samplerate to 1GSa/s and do not change anything but turn CH3 on.
Note also that I have adjusted small amount signal level between 2GSa/s and 1GSa/s and between SincON and OFF so that scope give same result using p-p measurement (average)
This do not change anything but with this method trigger levels where counter drops or not stay same.
Input frequency of course same 375. It is now 0.75*(sampling frequency/2)!
1GSa/s, Sinc OFF, vectors. Trigger level 57mV and freq counter stay stabile and correct.
1GSa/s, Sinc OFF, vectors. Adjusted trigger level 1mV up to 58mV so that counter just start drop.
1GSa/s, Sinc ON, vectors. Adjusted trigger level to highest level what give stabile counter. It happend at 57mV
1GSa/s, Sinc OFF, vectors. Adjusted trigger level higher until counter just start dropping. Noted that level is (agen) 58mV
Big question is: why it happend in same level independent of Sampling speed?
It must not happend if trigger is really generated from 2GSa/s (2x1GSa/s interleaved and when interleaved ADC's are 180 degree phase shifted.) data because naturally there worst case lowest level samples are higher.
Then I want look History for these things because there can see waveform adjust to trigger position. But also because normal History function is same what we also use for looking Sequence mode captured segments. (frames)
This is just scope running for fill history memory.
1GSa/s, Sinc OFF, vectors (lines) And here also trigger level adjusted just bit over point where we get stabile correct counter.
So it is set for 58mV and we can see counter drop some amount from 375MHz (375.008 ~ 375.009 is right)
Just stopped and just for one example, looked frame number 4 (waveform, segment or what ever name we give)
There can see one case where it may not trig. If wave what top is around LIST OFF menu selection it do not trig, quite rare but occurs. If look nearly left side same kind of.. it still may trig. (do not look line because scope do not look it, it look sample point ans only it!)
Then go forward and look bit more "frame" number 308. There is interesting situation. With veector (line) it adjust horizontal position right and between sample points just where linear interpolation go over trigger level.
Frame number 308. Now Sinc ON. Note shit to right so that Sinc interpolated curve is positioned to trigger position.
Still frame 308. Now display dots but Sinc still ON. Note dot position near trigger position.
Still frame 308. Now Sinc OFF and dots. (now dots position iss same as with vectors (dots) display mode.
Still frame 308. Now back to Sinc ON and dots. Shifted back to as images p and also n.
Siglent keep original sample points and it do not produce its own fake processed sample points
independent of what is interpolation and/or display mode.
One feature what I hope is that there is selection for highlight real sample points (specially for Sinc ON but also for vectors (lines) mode.
Still stay in same captured History. Now Frame number 320.
Sinc OFF, vectors
Still frame 320. Sinc OFF, display dots.
Frame 320, now Sinc ON. Display dots. If look carefully there can see tiny shift to right (is it one pixel (20ps)?). Because in this linear and Sinc interpolation is very near each others in trigger position.
Frame 320. Sinc ON. Display vectors.
It looks like primary trigger (or least counter trigger) is generated from 1GSa/s stream also when there is 2GSa/s interleaved mode in use. I can only suspect this, and with this method can not prove it with certainty. But indirect one evidence is how frequency counter start drop out because it do not get pulses. If these pulses are generated from 2GSa/s stream there is samples over trigger level in every single signal cycle. But, with 2GSa and 1GSa it start drop out some cycles just exatly with same trigger level when signal level is around same. With 375MHz there need be big difference if look worst case for one cycle with 1GSa and with 2Gsa. Difference is big. Also I do not believe they have generated separate trig pulses for counter and for primary signal trig. And, because this believe, I think counter trigger is one acceptable evidence.
(I think most know there is one ADC for two channels group. This ADC have internally 2 ADC. They can work separately giving out separate data streams (both give out 2 8bit stream) or they can operate in 1 channel mode where these ADC's are interleaved by clock (180 degree phase shift what means just inverted clock). Still they both give out 2 x 8bit data bus and whole 2GSa/s is now 4x8 bit data bus. More is explained in ADC data sheet)
Ed: attached image what show fine adjust between images t and u
There can see it use 20ps fine adjust step for image. (20ps is also TFT resolution limit when 1ns/div. One div is 50pixel)