Recall some time ago when Fujitsu Microelectronics shocked the IC design world with their amazing 56 GSPS 8 bit ADC back in ~2009, that was the last we've seen of any significant ADC surprises, maybe there are others lurking in China that we aren't aware of!!
If you look at the presentation material for that device you'll see the actual ADC was not much of a technical challenge. All the complexity in the device is handling the huge flood of data.
I guess it's no big secret that if you want to build a very high-speed ADC, you probably need an RF sampler up front, a massive demux stage and then you just interleave a couple hundred slower ADCs. You can draw the basic architecture on a napkin. Well, and then you just need to solve the endless practical problems that come with it...
Like mismatch (gain, offset, timing) calibration, clock distribution/alignment, the concrete demux/subsampling/buffering topology. I think one of the current Keysight ADCs has a secondary SiGe die that is mostly buffers for signal distribution. Power/thermal budget will be also a big concern all the time. A lot of small things have to go right in order to have a low-noise, low-distortion output instead of a complete mess. Sadly, marketing material tends to focus on impressing potential customers, not on providing interesting technical details to would-be-competitors. ![Popcorn :popcorn:](https://www.eevblog.com/forum/Smileys/default/EatingPopcorn.jpg.pagespeed.ce.yJ6TmC5fSa.jpg)
Although retired from IC design/layout mawyatt is still bound by NDA's. ![Lips Sealed :-X](https://www.eevblog.com/forum/Smileys/default/lipsrsealed.gif)
Sad it is too as there is so much to learn of his experiences in crafting the silicon we all use. ![Sad :(](https://www.eevblog.com/forum/Smileys/default/xsad.gif.pagespeed.ic.L3FGyzQrjB.png)
Probably will forget anything the NDAs cover anyway, memory is fading fast
![Huh? ???](https://www.eevblog.com/forum/Smileys/default/xhuh.gif.pagespeed.ic.6Nvt7O8a11.png)
Well I can say that if you have hind sight of a decade and half, and have never designed an ADC chip, or a chip of this level, then sure it looks easy to one that doesn't have to actually do it or be responsible for such (read put up your own $). Landing a man on the Moon happened long long ago, and today everyone knows how to do it, and yet nobody's been back!! That was a incredibly difficult task back in the late 60s and still is today, in spite of all the advancements and "know how".
Same goes for the Fuji 64GSPS ADC, I know Keysight did it and what it took and they didn't do it in 65nm
BTW they did develop a custom SiGe BiCMOS chip front end for the DSO, because the pure CMOS wasn't good enough!!
Anyway, this is a little off topic, so let's all hope Rigol's new HD DSO is a jewel. Dave has one now, so soon we'll get a glimpse of this puppy and how well it performs, hopefully he'll perform a 2 tone IMD test
![Wink ;)](https://www.eevblog.com/forum/Smileys/default/xwink.gif.pagespeed.ic.cldandycH0.png)
Best,