Replacement for Fluke 700013 IC (quad SPST analog switch)

[JoergR]

So the voltages appear ok at TP302 - in ratio 1:1 for ranges 0.2, 2, 20 and 1:100 for ranges 200 and 2000. The divider Z301 measures correctly as 18k, 2k.
The switches for 4WOhm, IDC and AC path U301D, U302D und U302C are all open - as should be I suppose.

Oddly, the switches U301A, U302A and U301B as well as U302B are also all open - so no signal appears at the input of Track and Hold Pin 14 of U301C. I would have expected that shorting any of these switches before the input to Track and hold would give sensible readings, but no such luck.

[Kleinstein]

The switches at the input to the S&H stage should turn on 1 at a time. In the non AZ mode, this may be just the 1 selected input. In the AZ mode there should be some switching between the zero reading U301C and the selected input. For 4 wire ohms this should be with U301D (for ohms sense low) instead.For some inputs there is also a precharge phase with U301A.  The sequence should be visible at the input to the S&H amplifier and also at the control signals to U301-U303.
Besides the CMOS switches also the JFETs Q311 7 Q315 have to switch - a possible defect would be U305 (= LM339 and thus cheap).

[JoergR]

Hm, the LM339 is probably ok, the FET also send the signal through. I checked the logic inputs to the U301, U302, U303 and they are totally off. I hadn't  done that before as with self tests and display working, I didn't suspect an error on the digital side. There is not a single high in AD0-AD7 that is supposed to come over the bus that appears on the inputs.... Other digital signals do appear to come in ok.

I checked the uC, U202, with the procedure described in the manual and the signals come out as described (the 1kHz and the interrupts etc). Since the display is working and the self tests are performed and even the right voltages appear on the test point 302 during the self tests, I guess the uC is good.

That leave U201 as the next suspect or the Adress Latch U219. I'll see what I can figure out there when checking the timing of signals between chips.

[JoergR]

So maybe there is progress. I checked the uC in my faulty device - a 8840A/AF and compared with my functional 8840A I found that the clock signal on pin#2 is very different. See the scope picture. Also, the clock pulses on the faulty device appear to have significant  jitter on them.

I tried exchanging the uCs between the devices. The uC from the faulty AF device would not work at all in the functional A. The uC from the functional A shows error 50 "guard crossing error" when placed in the faulty AF.

I'm a bit at a loss here as I don't know whether I should expect compatebility anyhow. Chips are marked different. The AF has the chip seen in the picture. The functional A has a chip marked Zilog Z8.

[Kleinstein]

Probing the clock signal is tricky, as the cystal part can already react to the extra proble capacitance. AFAIR there are also differences in the clock pins - causeing much of the trouble with the replacement earlier in the thread. So changing the µCs may not work, even if both chips are OK.

I the CPU is passing the self test, the AD0-7 lines should work OK, as reading the memory works. The switch specific part is mainly the CS2 signal for the latches.

The control signal for the switches has 2 paths: one via AD0-7 directly from the CPU and one directly from the ADC circuit. The settings from the CPU side may not update regularly, more like only with a function change. The other meter to compare should show the expected signal, if not in the service manual.

[coromonadalix]

what probes do you have on your scope ?

Do you have an x10 multiplier on them, it helps to get an higher impedance for measurements,  you have x100 probes too ...

[JoergR]

probes are Tektronix  P6133, 1:10, 15pF - they come with the 100MHz scope, but of course it all depends on the capacitance in the oscillator, doesn't? Probe capacitance must be small with respect to that, or?

[Kleinstein]

The capacitance at the crystal is in the 20 pF range - so even a rather low capacitance probe can disturb the signal and cause asymmetry in the loading. The clock seems to be good enough, as the µC seems to be running.

[JoergR]

So back to the drawing board. I went back to measure the digital signals on the switching chips, this time not with the multimeter as I had done the first time, but with the scope ...  they are ok and match what I measure in my functional device. I also figured out that in the 20V range, I can get a signal through to the track and hold. Then I get a decent signal on TP 103 - see the scope image and a reading that is stable albeit off by a factor of two. Note how the Track and Hold signal is not as symmetrical as in the functional device.

I then checked the Lm339 again, too. In contrast to the manual, it shows -26.5V on pin 12. Its supposed to have -5.5V at zero input. However, here it seems the defective 8840A/AF and the functional 8840A differ in construction. The zener CR303 is connected to -15V in the functional 8840A and to -30V in the defective 8840A/AF. So this could be by design and I just don't have the right manual - or the zener is broken. The CR303 in the defective 8840A/AF has the same marking 74 6 610 as CR309/11 which are both 3.9V Zeners that clamp the output of the track and hold. So I guess its by design.

That would be odd, though, as the LM339 is rated for symmetric supplies with +/- 18V max. Now +5/-26.5 doesn't exceed that differential, but still.

The PCB of the defective AF states 8840A/AF-3001 Rev C, the functional A is Rev E - both are dated 1983, though.

[Kleinstein]

The -26 V at pin 12 of the LM399 should not be a big issue.  The supply for the LM399 sould still be in the safe range. The difference would be mainly with the ability to also turn off a rather negative input signal, e.g. in the 4 Wire ohms mode or maybe (if supported) some ratio mode that uses the 4 Wire sense input as a 2nd input.
On the othe side a more negative voltage needs the switching JFET to withstand a higher gate voltage with a large positive input votlage. Worst case there many be up to some +24 V before the clamps engage. So with a -26 V supply the JFET would have to withstand -50 V gate to source. With a negative signal from the active signal this case may still happen though.

So I don't think the difference between the 2 vesions is that relevant, both should be OK, at least for the test / normal operation.

If the 20 V range kind of works, but the 2 V range not, this indicates a problem allread before the S&H stage, like with U301B

Getting at least some sensible signal out shows the U303 seems to be at least partially working. It may be interesting to see the input signal to the S&H stage constant in this test. It should change between 0 and the signal.  A factor of 2 error would also be visible on the scope - so is the factor 2 error allready at the input to the S&H stage or only at the output or maybe even a problem with the ADC ?

AFAIK the signal may be slightly asymmetric from an amplifiers offset, but not that much. 

[JoergR]

Hm, the ADC itself is most certainly not broken. When putting a short across TP103 (the output of Track and Hold) and Reference Low, I get close to zero counts, 16 to be exact in the 2V range (everthing below 35 would be fine). When putting a voltage below 2V between TP103 and Reference Low in the 2V range, the display shows the correct value with opposite sign, just as should be according to the manual. Changing ranges just changes the decimal point in the display, but not the digits.

I do think U301B is a problem due to the 2V range not working and I guess that's what brought me here in the first place. But let's leave that aside for the moment and focus on the Track and Hold if we can.

The input to the Track and Hold does appear to be working as intended in the 20V range. See the attached images. It oscillates between 1/10 of the input signal and GND as should be and no factor of 2 to be seen. This is true for both positive and negative input voltages.

One can also see the output of the track and hold in comparison - the high part of the signal is not amplified, but the low part of the signal is for positive voltages and the opposite is true for negative voltages.

The Z303 measures correctly. The digital inputs on U303 I measured and they correspond to my functional device. I wonder if some of the capacitances in T&H could be at fault or the current limiter (?) CL301 - it's high side is at zero volts. I'll make more comparisons with my functional device.

[Kleinstein]

The ouput of CL301 at around 0 V is about OK. It should about follow the input to the S&H stage with a little offset in the  0 - 1 V range.
If needed one could check the current from CL301 by looking at the drain voltage / input to the OP to see how much current is flowing.


As the track and settle phase seem to work I would expect the problem in the hold phase.   
It somehow looks like the signal in the hold phase is about doubled for some reason - which is odd, as there are no 2 equal resistors to make it double.
I see absolutely no reason how a broken capacitor could double the voltage - leakage would more like reduce the voltage. It would be more like having the switch U303 B not turning off. The divider would than be with 2 of the switches. 
The low side of C308 may tell the difference.

[JoergR]

Indeed, the signal on the low side of C308 - measured at U303-13/14/16 is different from the functional device. See the scope shots. It also shows a larger amount of ripple. But at this point, I'm pretty convinced that the switch ICs need replacements. I'll desolder them and see if I can pin down the defective switches and thus make sense out of the behavior observed. Thanks a lot to kleinstein for being so helpful!

[JoergR]

So here is the first one - U303. Only switch A seems to work as needed. Switch B never opens when a static high is on the latch and B, C and D drop about 0.6V when closed - indicating an on resistance of 1.7kOhm which seems a little excessive, but it could explain the false readings.

[Kleinstein]

1.7 KOhms sounds rather high for the on resistance.  With the large area used for the swtiches I would habe expected lower resistance, though the use in the ohms past suggests that the switches are pretty low leakage.  AFAIK the switches have a NMOS and CMOS part in parallel. The 1.7 K could be just one of those 2 halves and would than depend on the common mode voltage.  There is a slight chance the other half of the switch was damaged by overload from driving it too hard. Another possibly explaination would be some supply missing (e.g. broken bond wire or trace) so that maybe one polatiry never truns on and the other never truns off.
 
At least the 1.7 K would be high enough to explain why it still kind of worked for a gain of 2. The other involved switch would likey be similar resistance.


For the replacement it may be interesting to know of the latches are transparent latches reacting on the level like the 74xx75 (though other polarity) or D-type flipflops (like 74HC74) reacting on the transitions only. The chips are connected relatively direct to the CPU bus and thus get valid data only for a relatively short time.
The 74xx75 would definitely need an inverter for the latch signal, but still not so sure it would be right or if something like 74AC175 may be better.

[richipedia]

For the replacement it may be interesting to know of the latches are transparent latches reacting on the level like the 74xx75 (though other polarity) or D-type flipflops (like 74HC74) reacting on the transitions only.

Thank you for pointing that one out. In my opening post, I already mentioned that the original 700013 are transparent while the latch input pin is low. However, for my replacement, I chose 74AC175, which are flip flops, not latches. 
On my first veraboard prototype, I used 74AC573 latches, which do the job.

However, I do not know if the difference in behavior between latch and flip-flop is relevant.

[richipedia]

The DG411 is low resistance, but also has more leakage. The DG211 should be a lower leakage counterpart - AFAIK with the same pin-out  . Leakage can be a problem with the higher resistors.

I just tried to get an estimate for leakage current using a power supply at 5 V and a DMM in mV mode. The DMM has an input resistance of R_M=10 MOhm, so the voltage reading V_M should give me an indication of the leakage current I_L = V_M / R_M.
The DG411 switch I measured has ca. 0,05 nA ... 0,11 nA of leakage, which matches the typical figure in the datasheet.
On the other hand, the 700013 I measured has ca. 6 pA ... 15 pA of leakage. One order of magnitude less, just like the DG211. That's a good excuse to order some DG211.

Thank you again, Kleinstein!


Does anybody have a clue how relevant switch charge injection is for this application?

[Kleinstein]

I don't think the charge injection should matter very much. It may make a small difference at the S&H stage, but I would not expect very much difference as the capacitor is quite large (470 nF) - less charge injection should still be better. Chances are there is a correction parameter to compensate from the calibration.

The 74AC573 should be essentially the 6 channel equivalent to the 74HC77/75. It should be active high and thus the wrong polarity.  A tranparent latch has a kind of hold and an a transparent mode. The D-flip flop takes over the input only at the transition, and thus no tranparent phase, but a defiend time to copy the input data.
The HC175 should read the data at the positive edge and thus at the end of the  /CS2 or /CS3 pulse.  As far as I understand the bus protocoll this should be OK. However I don't know the bus with the /DS  /DM signals.

The /CS2 / CS3 signals come from an 74LS... , at least in the plan.  So the latch / flipflop should be a HCT or ACT version. The AC / HC version may no reliably detect the high level (an extra pull up may help as a quick fix).

[richipedia]

The 74AC573 should be essentially the 6 channel equivalent to the 74HC77/75. It should be active high and thus the wrong polarity.

I corrected for the wrong polarity using an inverter

The /CS2 / CS3 signals come from an 74LS... , at least in the plan.  So the latch / flipflop should be a HCT or ACT version. The AC / HC version may no reliably detect the high level (an extra pull up may help as a quick fix).

Another big trap for young players. The Z8 microcontroller also uses TTL voltage levels.

I think it's time for me to make a new replacement, using HCT, ACT or even LS logic and the venerable DG211
I might also make the board a little smaller. If i had the AC option PCB, it would collide with the replacement boards.

[JoergR]

Glad you join the discussion again richipedia. I'm learning a lot here about logic families - much like Montagues and Capulets it seems...
One question I still have:

BTW is the 700013 normally open (ie if an input is LOW is the switch OPEN)  
If that is the case then the DG212B (normally open) would be best because the DH211B is normally closed.

So why choose the normally closed version of the chip for the replacement?

For what its worth, when I checked the input signals to the 700013 chips in my devices, they would always switch several microseconds before the clock signal goes low and would stay at their level several microsecods until after the clock goes high again. From that, it seems that D-Flip-Flops would be just fine. But then, I only thoroughly checked in 20V mode and it may be different in other ranges.

[richipedia]

Glad you join the discussion again richipedia.

I guess that's what people do with a 3 year old thread about an unfinished project

One question I still have:

BTW is the 700013 normally open (ie if an input is LOW is the switch OPEN)  
If that is the case then the DG212B (normally open) would be best because the DH211B is normally closed.

So why choose the normally closed version of the chip for the replacement?

Please take a moment to look at my schematic: https://www.eevblog.com/forum/testgear/replacement-for-fluke-700013-ic-(quad-spst-analog-switch)/?action=dlattach;attach=1139450
The control signal for the analog switches comes from a NAND gate, so the switch should be conducting when the control signal is low and vice versa.
I should check what exactly happens at power on, to make sure that no opposing switches are turned on at the same time.

For what its worth, when I checked the input signals to the 700013 chips in my devices, they would always switch several microseconds before the clock signal goes low and would stay at their level several microsecods until after the clock goes high again. From that, it seems that D-Flip-Flops would be just fine. But then, I only thoroughly checked in 20V mode and it may be different in other ranges.

Maybe the latched inputs on the devices you checked do not change in between cycles. The fact that the switch output changes before the clock edge might be a hint that only the unlatched inputs have changed.

[Kleinstein]

Chances are high that both latiches and D-Fliflops would work. The switches are accessed similar to memory. So there is a CS pulse to activate the chip if a suitable address (actually a large block) and the control signals are there. The data should than be valid for a relatively short time (likely 0.2-1 µs range) and in this time the latching signal should get a short pulse.  The difference between a latch and Flipflop would be when the switched would change: with the latch the change would be just after the start of the pulse and the signal at the end of the pulse (which should be the same as at the start) would be preserved.
With a Flipflop the data just befor the end would be transfered to the switch - so a slightly later change, but essentially the same result.  The exact timing (10s of ns range) may be a bit different. It could make a difference with timing just at the edge -- however than it is not clear how fast the fluke chip is.
Both DG211 or DG212 could work - just need to have the suiteable logic chip in front (74xx00 = NAND or 74xx08 = AND).
The start up condition may indeed be a bit tricky. It may take quite some time until the CPU initiallizes the switches. So the initial state may be there for quite some time and multiple switches on could cause trouble.

[JoergR]

I had seen that you drive the switches with a NAND and so your design is fully equivalent in function - it couldn't function otherwise. I just wondered why you choose the combination NAND + Normally Closed switch over AND + Normally Open switch - just availability of chips or was there a deeper reason behind that? In fact, one could solder AND + Normally Open switch into your PCBs and it would work just the same, wouldn't it?

The difference may come only when someone applies a voltage on the input of the DMM without the meter being powered - then it might make a difference? That could occur if someone turns the multimeter off while the inputs are still connected or has forgotten to turn it on when the test circuit is already connected etc.

[richipedia]

I just wondered why you choose the combination NAND + Normally Closed switch over AND + Normally Open switch - just availability of chips or was there a deeper reason behind that?

An AND gate is made up of a NAND gate followed by an inverter, so the NAND gate has shorter propagation delay.
One could argue that a DG211 might be a DG212 with extra inverters before the inputs or vice versa, I honestly don't know.
Using the NANDs and the DGx11 seemed more natural to me, 3 years ago, but anyhow, we're already splitting hairs.

In fact, one could solder AND + Normally Open switch into your PCBs and it would work just the same, wouldn't it?

Absolutely.

The difference may come only when someone applies a voltage on the input of the DMM without the meter being powered - then it might make a difference? That could occur if someone turns the multimeter off while the inputs are still connected or has forgotten to turn it on when the test circuit is already connected etc.

I believe that the difference between the DG211 and the DG212 is basically that one of them has an extra inverter at the digital control input whereas the other doesn't. The actual switches are probably made of ordinary enhancement type FETs - no use of fancy depletion type FETs for the "normally closed" type, at least in my opinion. The terms "normally open" and "normally closed" probably are misleading.

Also, I just measured one of my DG411 ICs: switch resistance is ca 20 MOhm when unpowered

[edavid]

I believe that the difference between the DG211 and the DG212 is basically that one of them has an extra inverter at the digital control input whereas the other doesn't.

Usually the switch cell is driven by complementary signals from the input buffer.  To change the control signal polarity, those drive signals are routed to the opposite inputs of the switch cell.  No extra inverter is needed, just a wiring change.