As Tautech mentioned earlier, we were wondering why the SSA3032X PN is at the level it is at.
There seemed to be the potential for it to be better, given the high quality parts used, and at first glance most of the PLL's seem capable of lower phase noise performance.
Here are the PLL chips which were found in the teardowns:
1st LO: Hittite HMC703 + Z-Comm VCO + Doubler (3.9-7.1 GHz)
2nd LO: Hittite HMC835 (3.1 GHz)
3rd LO: Hittite HMC835 Divide by 4 (800 MHz)
Tracking generator LO: HMC835 (3.9 GHz)
ADC PLL: ADF4001
So what is limiting the phase noise to around -100 dBc/Hz at 10kHz?
I checked the datasheets for the phase noise specs, and this is what I take from it:
ADC clock:
The ADF4001 stuck out to me, as the datasheet shows it can only achieve -100 dBc/Hz at any offset at 200MHz - even though is is supposed to be 'Ultra Low Phase Noise'.
I think this is because it is an old part with a datasheet revision of 2003. The ADF4002 is a bit newer and has better performance but still not brilliant.
However, this PLL clocks the ADC, and I think it is tuning a 40Mhz crystal. This is a factor of
8 5 below the datasheet frequency, so theoretically
18 14dBc/Hz lower noise.
Also, I don't know how much effect ADC clock noise will have on the phase noise of the SA itself? Any comments?
And of course, the ADC clock does not influence the PN of the tracking generator, which is also a bit worse than -100dBc/Hz close in.
TG:
The TG takes the 1st LO and downconverts it using an HMC835 which must be running at about 3.9GHz. The HMC835 datasheet shows that it might be just a little bit better than -100dBc/Hz at 3.9GHz.
I thought the TG would be a good way to determine the PN of the LO. But it turned out that according to the datasheet the HMC835 hits about -100dBc/Hz @ 10kHz at it's operating frequency of 3.9GHz.
Since this is close to what I'm seeing then I still don't know what the limit is.
1st LO:
This is implemented by an HMC703 and a 2-4 GHz VCO, which is then doubled.
My first thought was that this would not be an issue. According to the datasheet the HMC703 can get close to -110dBc/Hz at 8GHz and around 10kHz offset.
(It only runs at ~3.6GHz in the SSA so would be ~6dB better than this, but since it is doubled in the SSA there is a 6dB penalty - so the 8GHz figure is close enough)
The caveat with this however, is that the HMC703 can only reach its best PN in 'HiK' mode, which uses a higher charge pump current. According to the datasheet this requires an active loop filter. The teardown shows a passive loop filter, so I assume that this mode was not able to be used.
Therefore the 1st LO may be only around -100 or -101dBc/Hz at the top end of it's sweep at 7.1 GHz. It may be about -106dBc/Hz at the bottom end of the sweep - 3.9GHz.
2nd LO:
The 2nd LO is another HMC835 at about 3.1 GHz, and so should be below -105dBc/Hz according to the datasheet.
So any improvements in the 1st LO past this level would not improve the SA function.
3rd LO:
This is divided twice from the 2nd LO and therefore should be 12dB better than the 2nd LO.
The phase noise of the SSA itself is fairly static until about 2GHz. Then it starts to degrade as the frequency is increased.
So I've concluded that either the ADC clock, or the 2nd LO, or both must be the limiting factor until 2GHz as they don't sweep and so their PN will not change with frequency. After that the 1st LO becomes the limiting factor as it is sweeping.
I was initially thinking that there was a single main driver of the PN, but now I don't think this is the case. I think that there are two, perhaps more, parts which limit the PN to about the same level.
I'm interested to hear any thoughts.
How do you determine when the ADC clock PLL quality becomes critical to the PN performance of a SA?
Anyone able to shed any light on the HiK mode in the HMC703 and any ideas why an active filter design would not have been used to take advantage of it?
Datasheets:
ADF4001 - ADC PLL
http://www.analog.com/media/en/technical-documentation/data-sheets/ADF4001.pdfADF4002 - replacement for above
http://www.analog.com/media/en/technical-documentation/data-sheets/ADF4002.pdfHMC835 - 2nd LO and TG
http://www.analog.com/media/en/technical-documentation/data-sheets/hmc835.pdfHMC703 - 1st LO
http://www.analog.com/media/en/technical-documentation/data-sheets/hmc703.pdf