OK, warranties are for losers so I cracked my brand-new GPD4303S open to see why this spike is happening.
First theory was that the service manual schematic has R727 going to +5VCC instead of +5VC as it should. This would have eliminated the intended 7mV offset in the voltage feedback signal and would prevent them from setting the voltage setpoint down to zero, or even better below zero to ensure that the integrator stage would saturate low instead of high when Q706 is engaged to disable the output. No joy here though, probing the board it appears that R727 is actually connected to +5VC as it should be and this is either a typo or an old schematic that has been fixed already.
![Sad :(](https://www.eevblog.com/forum/Smileys/default/xsad.gif.pagespeed.ic.L3FGyzQrjB.png)
So now I am pretty sure it is just a bad design of their disable circuit. With the unit powered on but output disabled, on my channel 3 I am seeing both V and I integrator outputs (U705) saturated high. This means that when the Q706 clamp is released at turn-on the main output FET will be turned hard on until either of the integrators can slew down into regulation. Looking at the inputs to the voltage integrator I see the feedback signal at ~5mV and the control DAC output at ~6mV.
On channel 4 the added offset to the feedback voltage is larger (9mV) due to the higher feedback gain. Looking at my channel 4 while still disabled the DAC output for the voltage control actually sits at about 2.5mV which is below the feedback signal of 9mV so it is able to keep the voltage feedback integrator saturated low when the output is disabled. I think this is why my channel 4 doesn't glitch at startup - the voltage control loop is starting from a disabled state rather than the enabled state that channel 3 was starting from.
The datasheet for the DAC (AD5643R) shows a 2mV typical and 10mV max for the zero-scale output, so it could be a part-to-part variation between my channels, but I think it is more likely a firmware thing that they don't drive channel 3 to a hard zero when off but they do for channel 4. It makes me wonder if a firmware update could fix the problem on the 4303S. If not that then I think a slight increase in the voltage feedback offset voltage might cure the glitch at the expense of a small setpoint error. Changing R727 from 1M to something about 700K would add 3mV to the feedback offset which should be enough to keep the integrator low when disabled. I think I might be willing to trade 3mV offset error for getting rid of this glitch.
However, for the 3303S there is no DAC for channel 3, just a set of resistor dividers to choose the setpoint and a saturated 2N3904 to clamp the setpoint while the output is disabled. I don't expect that transistor will be able to hold the voltage anywhere near the 7mV offset on the feedback signal, so for this model I expect that the integrator will always be saturated high when coming out of the disabled state. I can't really see a simple fix for this model.
Now to decide if I want to solder on my brand-new power supply or just put the case back on and live with the glitch...
![Confused :-//](https://www.eevblog.com/forum/Smileys/default/confused0024.gif.pagespeed.ce.5xOqKkq0Co.gif)