One issue that I did not find in the bug list, is the resolution of the trigger frequency display. I have a signal of 21.58Hz, it displays 21.0000Hz in the bottom. If it is not possible to measure it better than with 1Hz resolution, display at least 21Hz instead of 21.0000Hz. ![Broken! :-BROKE](https://www.eevblog.com/forum/Smileys/default/smiliey_scope_broke.gif.pagespeed.ce.z9RuKVWKjY.gif)
well, it's hard to say if this is really bug. The counter have 1Hz resolution, and i double checked the firmware so yes
there is way to set timeout for counter but i don't found anything resolution related. All i can see is 32bit long
data read directly from FPGA, and if i read it manually the smallest value is 1Hz.
Of course it's crazy, for high-unknon frequencies the counter is very good indicator to prevent user from
aliasing mistakes, but for lower freqiencies it's simply not good enough.
Sure, we can here use the measure, which does have 10mHz resolution, but yeah it would be nice to have the
counter as well with 10mHz resolution.
On the other side, there is up to 30ppm jitter so the couner would be not work very "stable". Sure, they could create a nice
reciprocal counter, and then change the menu/dispplay , and add maybe better oscillator (e.g. Crystek CCHD-575-25-100),
but then honestly the DSO would costs lot of more money. So i don't know how much space is there in FPGA, i can ask
to implement bette rcounter, but i can't promise anything.