Nope I haven't, thought about it then realized...why?
I still would have to deal with the kernel, devicetree, root data, filesystem... Nobody cares, why would I waste my time, f** it
I don't think you need probing:
Here's the F1C200s pinout asignment:
PIN GPIO NAME FUNCTION CONNECTED TO
6 GPIO96 PD0 TWI0_SDA(I2C) U9 5, LemonTree 118
7 GPIO97 PD1 LCD_D3 LCD
8 GPIO98 PD2 LCD_D4 LCD
9 GPIO99 PD3 LCD_D5 LCD
10 GPIO100 PD4 LCD_D6 LCD
11 GPIO101 PD5 LCD_D7 LCD
12 GPIO102 PD6 LCD_D10 LCD
13 GPIO103 PD7 LCD_D11 LCD
14 GPIO104 PD8 LCD_D12 LCD
15 GPIO105 PD9 LCD_D13 LCD
16 GPIO106 PD10 LCD_D14 LCD
17 GPIO107 PD11 LCD_D15 LCD
18 GPIO108 PD12 TWI0_SCK(I2C) U9 6, LemonTree 117
19 GPIO109 PD13 LCD_D19 LCD
21 GPIO110 PD14 LCD_D20 LCD
23 GPIO111 PD15 LCD_D21 LCD
24 GPIO112 PD16 LCD_D22 LCD
25 GPIO113 PD17 LCD_D23 LCD
26 GPIO114 PD18 LCD_CLK LCD
27 GPIO115 PD19 LCD_DE LCD
28 GPIO116 PD20 LCD_HSYNC LCD
29 GPIO117 PD21 LCD_VSYNC LCD
37 GPIO140 PE12 PWM0 LCD BACKLIGHT
38 GPIO139 PE11 Input R196, V USB detect from computer
39 GPIO138 PE10 SPI_MISO LemonTree 87
40 GPIO137 PE9 SPI1_CLK LemonTree 15
41 GPIO136 PE8 SPI1_MOSI LemonTree 90
42 GPIO135 PE7 Output LemonTree 88
43 GPIO134 PE6 Input Buzzer signal from LemonTree 21, R19
44 GPIO133 PE5 Output LemonTree 20, R101
45 GPIO132 PE4 EINTE4 LemonTree 22, R278
48 GPIO129 PE1 UART0_TX UART0
49 GPIO128 PE0 UART0_RX UART0
59 GPIO64 PC0 SPI0_CLK SPI NAND FLASH U2
60 GPIO65 PC1 SPI0_CS SPI NAND FLASH U2
61 GPIO66 PC2 SPI0_MISO SPI NAND FLASH U2
62 GPIO67 PC3 SPI0_MOSI SPI NAND FLASH U2
63 GPIO3 PA3 UART1_TX UART1
64 GPIO1 PA2 UART1_RX UART1
65 GPIO1 PA1 TP_X2 ?_?
66 GPIO0 PA0 Output V OTG enable
GPIO Table:
GPIO table (Page 14):
GPIOC
PC0 SPI0_CLK SDC1_CLK
PC1 SPI0_CS SDC1_CMD
PC2 SPI0_MISO SDC1_D0
GPIOD
PD18 LCD_CLK SPI0_CS EINTD18
PD19 LCD_DE SPI0_MOSI EINTD19
PD20 LCD_HSYNC SPI0_CLK EINTD20
PD21 LCD_VSYNC SPI0_MISO EINTD21
GPIOF
PF0 SDC0_D1 DBG_MS
PF1 SDC0_D0 DBG_DI
PF2 SDC0_CLK UART0_RX
PF3 SDC0_CMD DBG_DO
PF4 SDC0_D3 UART0_TX
PF5 SDC0_D2 DBG_CK
So, SD0 pins seem to be free (PF5-PF0, pins 53-58).
There're no vias in these pads, and there's no space under the SoC to put them, so they seem to be completely unused.
Looks like they routed the unused pins to test points, just like UART1... good.
SD1 pins (PC0-PC2) are used by SPI0, for the SPI nand.
Alternative SPI0 pins are used for the LCD (PD18-PD21)
The easiest way to see the use of a pin is by reading Pn_CFG registers on the livesystem, then check the tables on the
User manual (Page 117)
The registers can be accesed like normal memory from linux, so:
- PIO Base addr: 0x01C20800
- PF only has Configure Register 0 (Offset: 0xB4)
# devmem 0x01C208B4 32
0x00373733
Decoding 0x00373733:
RESV DGB_CK RESV DIS RESV DGB_DO RESV DIS RESV DBG_DI RESV DBG_MS
000000000 011 0 111 0 011 0 111 0 011 0 011
So SD0 pins are used by the debugger. I don't think it's important, I'm sure you could set this register to interface the SD.
Reg bits for SD: 010 0 010 0 010 0 010 0 010 0 010
# devmem 0x01C208B4 32 0x222222
At least, I've tried and didn't got any issues.