Heres three waveforms created on easywave just to test ,the first two have 8192 samples ,the last has 16384.
What Im thinking is that ,maybe by somehow changing or rearranging the memory sample banks the fpga chooses from we could come up with better figures for THD, jitter or aliasing ,which ever you want to call it . This thread is so long I often end up reading back stuff that Ive forgotten ,but Zov as far as I remember did suggest something along similar lines ,
could for instance starting and finishing a sample not at the zero crossing points but somewhere else in the cycle help , could different frequency samples be used when the frequency isnt set to a divisor or multiple of 250mhz . Its 14 bit at the end of the day I think best case scenario a signal to noise of about 80db is possible ,at an unfavarouble setting of the controls maybe this worsens to about 50-60db.
Just looking across the specs on the 6800 ,they say its now got resolution down to 100uV ,where the minimum step in the 6600 is 1mV, so maybe they have managed to squeeze something more out of it .