Ok so I hit some luck.
Probing around in the internal headers of the DS1000E series has some very interesting signals on them. For the purpose of this discussion though, I found the trigger output.
Harvs,
that pin could be sync to logic analyzer module as well, and not trigger out.
Another thing is, with long memory enabled you should got different values, a real trigger out should get affected by sample memory changes.
Anyway, you can do another one test (maybe you ran it already?), apply only single pulse, then two, then burst, etc and compare it with the "trigger out" you found,
if that's really trigger out then there must be no difference (on each pulse/burst you need to get signal there).
Ok so I hit some luck.
Probing around in the internal headers of the DS1000E series has some very interesting signals on them. For the purpose of this discussion though, I found the trigger output.
Nice find!! I'm rather amazed no one has located this before. ![Smiley :)](https://www.eevblog.com/forum/Smileys/default/xsmiley.gif.pagespeed.ic.R8GFI-pF6f.png)
probably nobody was really looking for, but when you check attached picture you will see that Rigol is having some kind of
phase/trigger delay? circuit (i found it as well in older Rigol series, as well in ATTEN, Tekway A series, Hantek hw1005,
Siglent. Attached schematic of Hantek's version of that circuit as well, Rigol is almost the same).
That could be another place to look for trigger out.
Something else to watch (for those who checked with "edge disapears" way) is not to get fooled with display refresh sync,
Rigol DS1000 seems to have display refresh rate menu, when value changed the estimated wfms/s should not change when
the DSO-core is in FPGA only, when in DSP as well then it should change when DSP running single thread, but when more threads then
it should remains (almost, there can be some overhead) the same (as the display thread should have no influence on capture/postprocess thread).