I read much of the BSTJ paper. They give two typical applications: a delay line (probably of interest as delay matching has always been a huge concern for Bell?), and a particularly high "Q" filter.
The delay is pretty ordinary, as from our perspective it's simply a macroscopic BBD, or an analog (continuous voltage, discrete time -- switched capacitor) circular buffer. Not bad for 1960, though doing it via mechanical means is kind of barbaric, even for them (but hey, transistors were still expensive back then). The circuit used is perhaps a bit unexpected: they go through the derivation of the impedance of a single all-capacitor switch, showing it has the characteristic of a stub transmission line, with leakage resistance equivalent to termination resistance. The implementation of a delay is then obvious: put it in a feedback network.
The bandpass filter was implemented with diode gates and transistor multivibrators, running at 25kHz. They give N = 4 (so, operating in quadrature -- they give a note earlier (p.1328) that two channels are possible given this condition, which makes sense as half the channels here are essentially complementary), though a full circuit isn't given (presumably the diode gates are decoded one-hot, as Fig.10's switches suggest, in which case d1 = d2 ~= T/4). They don't show how bad the sidebands are, but it's clear that it won't be great: N is small. N seems to give the sampling ratio, as we expect from ordinary/modern DSP work. So, larger N simply affords a larger ratio between passband and stopband, and antialias filters are required in the usual way.
A downside: at high frequencies, we may find no choice but to use a pile of PLLs to generate the phases. For example, say we want an 8-path filter centered at 144MHz. Well, we need Fclk = 8*144MHz to use an 8-way counter-decoder here. Possible, certainly, but well beyond the reach of average 74HC logic. Well, 144MHz itself isn't exactly in HC bandwidth either... maybe not a great example, but you can see there's plenty of range where a given logic family might be suitable, but for the master clock frequency required, or the pulse width demands.
I wonder what you'd use for that, actually; maybe ECL, and just (schottky) diode gates, and make sure the signal amplitude is low enough to avoid bleed-through? So, we'd just get whatever dynamic range we get that way. 74LVC I don't think is quite fast enough for that, but it would be close? The uh, whatever the next lowest voltage, newest CMOS family is after that one I forget, would probably do. For sure, an IC would be able to pull this off, netting say a volt or two of dynamic range, and clean (NMOS or other) switching.
As for smooth LO input (p(t) and q(t) being sinusoidal, or nearly so), it seems it doesn't give images; which makes sense, it's essentially a baseband quadrature (or more) receiver. If only it were easier to perform highly [bi]linear mixing...
Tim