It seems to me that there should be a relationship between system response time and sampling rate. What values can be obtained with the available ADCs?
What response time you're talking about?
Do you have specific requirement for the filter phase delay?
There is relationship between bandwidth and dynamic range. High speed ADC has wide bandwidth and it's dynamic range/bit resolution is specified for a full ADC bandwidth, which is a half of sampling frequency:
bandwidth = sample_frequency / 2
If you apply bandpass filter, you're cut off part of noise power and it leads to lower noise floor and dynamic range gain. This is known as processing gain:
processing_gain_db = 10 * log10( input_bandwidth / output_bandwidth )
for example, if you're using 125 MHz 16 bit ADC and digital filter to get 3 kHz output, you will get:
processing gain = 10 * log10( 125000 / 3 ) = 46.2 dBprocessing gain = 10 * log10( 62500 / 3 ) = 43.2 dB
ADC has 125 MHz sample clock, so it has 125/2 = 62.5 MHz bandwidth.
ADC has 16 bit, ideal 16 bit ADC has 16*6.02+1.76 = 98.08 dB dynamic range (real ADC has a little worse).
For 3 kHz output you will get about 98.08 + 43.2 = 141.3 dB dynamic range.
But note, your dynamic range increasing at the bottom due to noise power filtering.
The max ADC input power limit remains the same.
So it's hard to say if you can replace analog filter with digital processing, because it depends on the total power of unwanted carriers within 3...10 MHz bandwidth, which you want to cut off.
For example, if you're needs to get 3 kHz at 4 MHz and 3 kHz at 6 MHz, but there is very strong carrier at 5 MHz which leads to ADC overload, you will need to add attenuator to avoid ADC overload from 5 MHz carrier, but as a side effect such attenuator also will reduce dynamic range for 4 and 6 MHz carriers.