The two ltspice models i use you can find here .
http://ltwiki.org/?title=Components_Library_and_Circuits just click on the 7.-opamps . and you will find lm324/ns model there .
on this same page both the lm324/ST and lm324/ns are in the "A Large LTspice Folder from Bordodynov" in the "extra" folders of that download . These are what I used .
On how did I came up with these values , It was from both a bit of experience and from looking at the bode plots of these circuits . If you want to do the bode plot of your circuit try the "loopgain2" method you will find in the examples directory of lt spice .Bode plots are fairly easy to do (in spice anyway ) but youl need to do a bit of reading and practice to interpret them and use them (but basically it's phase shift at the 0db gain crossover point that's the important bit ) .
What your trying to do here is get a stable but as fast control loop as you can ,so this means adding as little compensation as you can get away and still be stable .(it's very easy to stabilize any feedback control loop just by keep adding more compensation and reducing it's bandwith to lower values but then you have reduced it's abilility to react fast to any changes which is the whole point of the feedback loop in the first place,.).
An easy way for most hobyiest and beginers to check control loop stabilty with out having to do Bode plots(and it works for 99% of the time) is to just do a step load response and you can get an good indication of the phase margin ( stabilty) that way . the nice thing about this is that you dont need expensive equipment and to can do this in both Ltspice simulation and on the real circuit , you can then compare the results . (to do this in ltspice on your circuit just step the load voltage souce (V2) rapidly a few volts in your simulation and then plot the response across the current sense resistor (R1) ).you can then compare to chart like I have posted below to get the phase margin, the amount of overshoot/ringing indicates phase margin ,you aim for about ~ 60 deg margin for a optimized loop .(but you should also test under the worst working case senariou your likely to see to check is still stable (not oscilating but will have much reduced phase margin). :-that is with a resistive load in the Drain of Fet for Electronic load type circuits like yours ).
Or you could of course avoid all the above and just copy what everyone else does .It's up to you
Anyway It's sunday ,so my day of rest so enough typing for me today
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Good luck .