power decoupling myths

[OwO]

No doubt that simulations are useful for sanity checking your work, and I use them to give a rough ballpark answer to "is this design workable" and to find pitfalls of a design that I missed (e.g. potential stability issues), but my point is you should never trust it to give an authoritative answer to "how well will this perform" or "are these vias useless". Only real world experiments can say for sure. So to tell people "get a simulator, it will teach you how to do good layouts" is bad advice, and IMO that money is better spent on good TE instead, or even just experimentation and prototypes.

[TheUnnamedNewbie]

Another thing I learned: Discrete components are pointless to do any decoupling past a few hundred MHz. Even if you ignore any layout effects, the interal ESL of a 008004 cap makes it's self-resonance frequency be around the 100 MHz range. You just can't get around that without using special bonded capacitors meant for RF/MMIC applications. And to be frank, even if you could, your bond wires will just ruin that too. Just trust that the IC guys know their stuff and take care of decap past 100 MHz.

Or actually you know, make real life measurements that will tell you a typical 0402 1uF capacitor has good decoupling up to 6GHz. Or if you don't have the TE maybe manufacturer's graphs will convince you? http://weblib.samsungsem.com/mlcc/mlcc-ec-data-sheet.do?partNumber=CL05A105KA5NQN

You are already halfway to being enlightened. The first half is knowing that "best practices" are BS, the second half is knowing simulations are BS.

I stated clearly that the self-resonance was at a few hunderd MHz. Your example shows that the self-resonance is at 10 MHz (and that is usually without any pad and so on included, which will only push it further down.

If your simulations do not match your measurements, one of the two is done poorly. This can be misunderstanding how to do them, bad simulation setup, bad material properties, etc. We have desigend VCOs at 600 GHz that had a shift between measurement and simulation in the tens of MHz. So please go tell someone else he doesn't know what he is doing and that my simulations must be bad.

Now, back to my example and clarifying why there is little use in having those tiny capacitors and going nuts about your vias:

A bondwire of 1 mm is what, about 100 mOhm? Probably a good bit more at high frequencies due to skin-effect. Typical rule of thumb for bondwire inductance is 1 nH per mm. Plug that in and you find that you will have an impedance of about 600 mOhm at 100 MHz. So past 100 MHz, your chip is not gonna see a much lower supply impedance than 600 mOhm anyways. It doesn't matter if your supply impedance is 100 mOhm, 10 mOhm , or 1 nOhm at 1 GHz - your chip will just see the (at that point 6 Ohm) bondwire. Anything past a few tens to hundreds of MHz is for on-chip decoupling to solve. Sure, you can do better, and you shouldn't allow it to get horrible, but most of your decap will be done on-chip anyways.

And before you say 'But RF transistors!' - Usually, you slap a big fat inductor on your supply of the transistor to tune out the internal capacitance anyways. Probably the internal parasitic capacitance of your device is going to do more 'decoupling' than any external decap you add.

Simulations are as good as your models are. I'm kind of questioning the models he used.

I used high-performance models from multiple manufacturers: Samsung, TDK, Taiyo Yunden, Murata, as well as from Modelithics. They pretty much all tell you the same story, and line up with what their websites tell you. And the software and methods are the same used to design high-performance filters on PCB - there might be a few percent error, but it's not going to be an order-of-magnitude difference.

[OwO]

I think we went from talking about digital ICs to RF circuits many posts ago. The #1 use case for a low impedance point on the power supply network in a RF circuit is for interference rejection, and there no bond wires come into play.
See for example this power supply filtering layout:


This is good to 6GHz, and if your models are good enough you should be able to see for yourself. The capacitors are CL05A105KA5NQN. The distance to ground plane is 0.2mm and material is FR4. You can't make a blanket statement that discrete caps are no good beyond a few hundred MHz.

[OwO]

the internal ESL of a 008004 cap makes it's self-resonance frequency be around the 100 MHz range.

The problem with that is there is no "internal ESL" of a capacitor. Any inductance is due to the physical layout and the path that current has to follow. A wire by itself doesn't have defined inductance, and only the combination of a wire + ground plane does. I showed a few posts ago how to minimize the layout effects and in that example the impedance is mainly only due to the stub of transmission line between the DUT and the capacitor (which can be minimized by making it wide). I'm sure the manufacturer used a similar layout when characterizing the capacitor.

The SRF of a capacitor is not important. You only care about the worst case impedance across a frequency range.

[TheUnnamedNewbie]

I think we went from talking about digital ICs to RF circuits many posts ago. The #1 use case for a low impedance point on the power supply network in a RF circuit is for interference rejection, and there no bond wires come into play.
See for example this power supply filtering layout:
(Attachment Link)

This is good to 6GHz, and if your models are good enough you should be able to see for yourself. The distance to ground plane is 0.2mm and material is FR4. You can't make a blanket statement that discrete caps are no good beyond a few hundred MHz.

I never said that discrete are no good at all. I said, and I quote:

Discrete components are pointless to do any decoupling past a few hundred MHz

The topic of this is also 'power decoupling myths'. If you read my posts, you'll notice all I talked about was power supply decoupling. You are always gonna find special cases. But this entire thread of posts before was clearly about powersupply decoupling, and your posts and images implied your way was needed.

And don't try to now straw man me into being wrong by throwing the old 'but inductors need a loop' argument. You know all to well what I meant with ESL, and if you don't you aren't a very good RF engineer.

And SRF is important, because it gives you a nice point to know 'It all goes down-hill from here'.

the internal ESL of a 008004 cap makes it's self-resonance frequency be around the 100 MHz range.

I showed a few posts ago how to minimize the layout effects and in that example the impedance is mainly only due to the stub of transmission line between the DUT and the capacitor (which can be minimized by making it wide). I'm sure the manufacturer used a similar layout when characterizing the capacitor.

Making a setup to calibrate out the inductance of your test network is trivial. We do it all the time, because that is what VNA calibration is all about. That PCB inductance is thus NOT included in the models, because if it were, the models would be all but useless for design work.

[OwO]

"Discrete components are pointless to do any decoupling past a few hundred MHz" is misleading, since it's implying it's the discrete components that are no good, when the real matter is the bond wires defeating any decoupling attempts.

"the internal ESL of a 008004 cap makes it's self-resonance frequency be around the 100 MHz range" is correct on its own, but within the context a reader will think you mean the internal ESL of a discrete cap makes it useless above a few hundred MHz, which I explained is incorrect. Again, SRF of 10MHz is irrelevant when the impedance is still < 5 ohms at 6GHz.

Anyway, I don't get the appeal to authority bringing up your 600GHz design, because you are designing on a process with feature size possibly 1000x smaller than on a PCB, in other words a 6GHz design on an ordinary FR4 PCB is no easier layout-wise than a 600GHz design on a 1um process. It's like telling someone to design a 1GHz circuit using a wire-wrap process that his design is "DC" to you who designs stuff with geometries 10k times smaller.

[TheUnnamedNewbie]

"Discrete components are pointless to do any decoupling past a few hundred MHz" is misleading, since it's implying it's the discrete components that are no good, when the real matter is the bond wires defeating any decoupling attempts.

Explicitly situation the context of a statement is clearly misleading, unlike, say, showing pictures with a big red cross under a layout that is perfectly fine in 99.9% of cases, and a green check mark under a layout that has arguably way to many vias that will just make the layout a hell in any high-density situation.

[iMo]

I've quickly looked at the pdfs in the first post. I did a recommendation on "3 capacitors in parallel" many times here. I saw that in an app note of ADI (as far as I can remember) long time back.

One of the issues I see with the attempt to debunk the myth is following - the ADI recommendation (and mine here as well) said explicitly you have to use 3 capacitors in 1:100 ratio, like 100p||10n||1u, etc..
Not in 1:10 as it has been elaborated above..

[OwO]

The takeaway from the discussion above is that the capacitor values are not that important, it's the overall layout, and the fact that the bond wire in a typical IC defeats your decoupling attempts and you will do just as good with a single 1uF or 10uF cap in the common case of decoupling a digital IC. But if you are doing any other kind of design, the best layout should be decided on a case by case basis.

[Siwastaja]

Yes, the point is, C value isn't important as long as you have enough. After you satisfy this minimum condition, you select by L.

In the past, large enough C had kind-of too much L, so you paralleled larger and smaller C to get "best of the both worlds". Said types had enough ESR to make the SFR low-impedance dips not too shallow, but combine in larger areas without so much risk of oscillation.

Now, you get large enough C with small enough L, just buy a bog-standard small-case MLCC. Say 0.47uF 0402 part, for example. So there is no reason for the paralleling trick.

Furher, the ESR of modern MLCC is so low, making Q high, that the parallel combination contains new extra risk of oscillation.

[iMo]

When you look at the "V" shaped frequency characteristics of the capacitors - smds of any shapes and values almost all manufacturers show it in their datasheets, it is clear, at least for me, that paralleling more capacitors makes sense. Not in 1:10 ratio, as the "V" shapes are too close each other and it really makes no sense - but 1:100 makes sense.. Talking RF here, not the power supplies, however..

[thm_w]

When you look at the "V" shaped frequency characteristics of the capacitors - smds of any shapes and values almost all manufacturers show it in their datasheets, it is clear, at least for me, that paralleling more capacitors makes sense. Not in 1:10 ratio, as the "V" shapes are too close each other and it really makes no sense - but 1:100 makes sense.. Talking RF here, not the power supplies, however..

Did you read all of the first link from OP?

Unless you are targeting a very specific frequency, the simulation shows its no better.

[exe]

I'm confused. For years I was reading that a solid ground plane is a must for a high-speed or mixed-signal design. So, it's a lie?

Also, what do you guys think of capacitor bypass sequencing? (http://www.sigcon.com/Pubs/news/9_07.htm). In terms of isolating rest of the system from "noisy" components. It's very hard to find info on the topic, even harder to find a source with measurements. Most sources either provide "best practices" without going into details, or provide only theory, but not practical measurements, which makes it suspicious for me as I've seen people go very far in delusions (e.g., audiopholery).

[David Hess]

I'm confused. For years I was reading that a solid ground plane is a must for a high-speed or mixed-signal design. So, it's a lie?

It is not exactly a lie, but there are places where a ground plane is either not required or inappropriate.  A ground plane provides the most direct route for return currents but if that can be provided in other ways, then it is not needed, and it is inappropriate where return currents must be directed around sensitive nodes.  The alternatives require careful attention to return currents, ground loops, single point grounds, and other such things.

[T3sl4co1l]

Also, what do you guys think of capacitor bypass sequencing? (http://www.sigcon.com/Pubs/news/9_07.htm). In terms of isolating rest of the system from "noisy" components. It's very hard to find info on the topic, even harder to find a source with measurements. Most sources either provide "best practices" without going into details, or provide only theory, but not practical measurements, which makes it suspicious for me as I've seen people go very far in delusions (e.g., audiopholery).

Ineffectual, for similar reasons as the, aherm, discussion, above.  Which, I'm certain my explanation will get misinterpreted just as poorly...

The attenuation from pin to plane, for either connection shown, is minuscule.  The trace connected one will have a little more than the other.  It is easy to calculate what the cutoff frequency will be (given some other assumptions), and subsequent impedance peak seen at the IC pin.

The real question is, are those values -- the impedance and frequency -- meaningful?  Are they desired?  Do they meet a specification?  If so, what?


Note that there are two different goals:
1. The impedance at one port of the PDN (power distribution network)
2. The attenuation from that port to other ports (examples: other device power pins, conducted EMI on cables, radiated EMI to space).

In general, simply having a low supply impedance at a pin will give good attenuation for a given current: V = I*Z.  But it's a zeroth order relation: it doesn't have any scaling or anything, it is what it is.

If you can't brute-force the impedance, and your attempts to do so are frustrated by unintended resonances (leading to peaks in pin impedance, and peaks in transmission through the network), you will have found the limit of that method.

To do better, you need to design the filter.  Specify port impedances, and the minimum attenuation over some frequency range.  Notice zero and infinity are NOT valid inputs to this process!  You are therefore forced to consider what impedances and attenuations are actually required, and have to consider what is actually possible.  A meaningful process ensues, and component values and trace/plane geometry can be solved for.

To put it differently:

The above article is wrong, in a completely separate way.  The question we must ask is, not whether one or the other is better, but what are the properties of both, and how can we design those properties?

The simplest way to get high attenuation -- good filtering between ports -- is to use inductors, or CLC ladders; lowpass filters in general -- to connect between them.  The impedance of these filters must be suitable for the source and load, and the cutoff and attenuation are defined by the frequencies and attenuation of interest.  Additionally, we should give some thought to grounding (avoiding ground loops) and shielding, particularly when the desired attenuation is very large (say >60-80dB).

With a fully specified procedure, we have no fear of encountering the situation that a naive designer might find themselves in when they, say, randomly pepper 100uH chokes throughout a design -- sure the attenuation might be great, but the impedance is massive, and must either be balanced by generous bulk filter caps (lossy ones at that), or employed only for high impedance loads.  And with a "random peppering", the attenuation attained might be all over the board -- excessive (wasteful of BOM cost and board area) in some areas, yet insufficient in others.

This is equally valid at 60Hz as it is at 60GHz.

Tim

[OwO]

If you have the luxury of high layer count boards with very close planes, then going to the plane is usually what you want to do. But if not, then this is probably the best decoupling you can get:


You can not make a blanket statement that capacitor "sequencing" is ineffective, or that you should always sequence capacitors. There is no substitute for simply having experience by doing lots of experiments, measurements, and trial and error. If you are new to high speed design, there is no better way to shoot yourself in the foot and lull yourself into a false sense of security than by playing around in a 3d EM simulator (and I learned this by experience too). Do some shitty designs, make mistakes, understand why they fail, make bodges on PCBs and do measurements to understand how the physical world really behaves.

[Siwastaja]

When you look at the "V" shaped frequency characteristics of the capacitors - smds of any shapes and values almost all manufacturers show it in their datasheets, it is clear, at least for me, that paralleling more capacitors makes sense. Not in 1:10 ratio, as the "V" shapes are too close each other and it really makes no sense - but 1:100 makes sense.. Talking RF here, not the power supplies, however..

Yes but your circuit likely does not draw currents at those exact frequencies defined by the "V" valleys. Your circuits want low impedance between those V dips as well. If you are able to provide low enough impedance through the whole spectrum, then adding a few additional even-lower dips is completely meaningless.

[mawyatt]

FYI, 3GHz is DC for @TheUnnamedNewbie.  Not sure how familiar you are with his work.

the second half is knowing simulations are BS.

Ah yes, simulations can never be correct so why even bother!  It's not like anyone has ever built anything of significance, let alone had it work perfectly the first time, using a filthy simulator!

Tim

Tim,

Well I also got a good laugh

I'm sure Maxwell didn't know anything, neither did Larry Nagal (SPICE), or Ken Kundert (Cadence)

Best,

[mawyatt]

Ever since I put a number of layouts into actual EM solvers I realized that everyone on the internet who says 'you have to do it this way' is wrong.


Just trust that the IC guys know their stuff and take care of decap past 100 MHz.

On the IC side of things where I just retired from we always tried to simulate the effects of poor off-chip supply decoupling and included as much decoupling as possible on the chip. Circuits were used that were less supply sensitive like differential circuits if practical. We often used multiple regulators (Point of Load Regulation) because of decoupling, many times just getting to a chip pad wasn't practical, so a local regulator was utilized. This isn't restricted to analog/RF/MW circuits, with a massive array of digital gates all working in lock-step with the clock, very large di/dt are created and tax the decoupling schemes, both on and off chip.

Best,

[OwO]

That was in response to this:

If you really want to understand and know, do yourself a favor: Stop going by some online forum post telling you what to do, and go rent/buy a copy of an EM package for a few weeks, and actually play around in that.

Simulations will not help you "understand and know". Maybe if you are already experienced and already know how to improve a layout, sure. But to suggest trying to *learn* by playing in a simulator is bad advice and will lead a beginner the wrong way. Someone experienced like you know instantly when a simulation is unphysical, either due to setting up the wrong conditions or bad models. Someone inexperienced with RF layout needs to do everything EXCEPT go buy an expensive 3d EM simulator and spend hours going down rabbit holes of unphysical and unrealizable designs, without even realizing why their design that performs perfectly in simulation is impossible to realize in real life.

I also don't get the point of saying 3GHz is DC to you, because a RFIC has geometries at least 1000x smaller than a PCB, so a 600GHz RFIC circuit is like laying out a 600MHz circuit on a PCB. Not the same thing of course, the basic circuit elements you have available to work with are completely different, but layout wise your elements at 600GHz are electrically small, while at 6GHz the simple via distance or the inter-plane distance on a PCB is getting significant relative to a quarter wavelength.

[OwO]

For a beginner wanting to start with RF design, start with pen and paper. Start with deriving the transmission line equations (telegrapher's equations) to understand 1D wave behavior, and work your way up to wave equation in 2D/3D and maxwell's equations. You need to be able to visualize how a changing electric or magnetic field give rise to each other, and how fields are related to currents and charges. None of this insight can ever be gained by playing in an expensive EM simulator. I recommend just going to your local university and auditing the high frequency electronics and electromagnetism classes up to 4th year level. None of these classes will involve a 3D EM simulator, maybe RFSim99 at most. RFSim99 is useful for checking basic circuits, but again ONLY if you already understood the underlying transmission line theory beforehand. Same story with full EM simulators, don't even touch them until you can fully visualize EM wave behavior and know maxwell's equations by heart.

[Alex Eisenhut]

I'm a big fan of the Smith Chart. In any case you'll need to know about it to interpret VNA displays.

[TheUnnamedNewbie]

That was in response to this:

If you really want to understand and know, do yourself a favor: Stop going by some online forum post telling you what to do, and go rent/buy a copy of an EM package for a few weeks, and actually play around in that.

Simulations will not help you "understand and know". Maybe if you are already experienced and already know how to improve a layout, sure. But to suggest trying to *learn* by playing in a simulator is bad advice and will lead a beginner the wrong way. Someone experienced like you know instantly when a simulation is unphysical, either due to setting up the wrong conditions or bad models. Someone inexperienced with RF layout needs to do everything EXCEPT go buy an expensive 3d EM simulator and spend hours going down rabbit holes of unphysical and unrealizable designs, without even realizing why their design that performs perfectly in simulation is impossible to realize in real life.

So, just some comments on this:

- I figured that someone at this level of engineering, where they start to really ask questions of how power supply decoupling and filtering works, is no longer a beginner. Hence I stand by my statement that they could gain a lot of knowledge from simulating this kind of structure. At least a lot more than just trying to make sense of the 200 contradicting guidelines online.

- Simulations with PCBs at frequencies up to a few GHz, in my experience, never show nonphysical behaviour unless you are just purposefully messing up the meshing settings. Just runing through the few tutorial examples should teach you all you need to know to simulate some decap networks. This isn't simulating some 10-pole comb-line filter or SIW or multi-band stacked patch antenna. Just a capacitor and a few pieces of copper wire.

I also don't get the point of saying 3GHz is DC to you, because a RFIC has geometries at least 1000x smaller than a PCB, so a 600GHz RFIC circuit is like laying out a 600MHz circuit on a PCB. Not the same thing of course, the basic circuit elements you have available to work with are completely different, but layout wise your elements at 600GHz are electrically small, while at 6GHz the simple via distance or the inter-plane distance on a PCB is getting significant relative to a quarter wavelength.

My latest work involves a 100-190 GHz PCB vivaldi antenna, and a 110-170 GHz 4-layer orthomode waveguide coupler. All on PCBs. Not even that extremely fancy PCBs, regular HDI boards. Heck, I don't even have frigin blind vias! The 600 GHz transmitter was just an example.

Just because I work in a team that does RFIC design does not mean that I only do RFIC design. And if you really think making 600 GHz RFICs in CMOS is that trivial, be my guest, and let me know when you pull it off.

For a beginner wanting to start with RF design, start with pen and paper. Start with deriving the transmission line equations (telegrapher's equations) to understand 1D wave behavior, and work your way up to wave equation in 2D/3D and maxwell's equations. You need to be able to visualize how a changing electric or magnetic field give rise to each other, and how fields are related to currents and charges. None of this insight can ever be gained by playing in an expensive EM simulator. I recommend just going to your local university and auditing the high frequency electronics and electromagnetism classes up to 4th year level. None of these classes will involve a 3D EM simulator, maybe RFSim99 at most. RFSim99 is useful for checking basic circuits, but again ONLY if you already understood the underlying transmission line theory beforehand. Same story with full EM simulators, don't even touch them until you can fully visualize EM wave behavior and know maxwell's equations by heart.

I fully agree that people starting with RF design should start there. That is also what we teach. But this was never fully on RF performance - this was power supply decoupling. Most cases, the caps are actually close enough to the IC's you are decoupling that you can ignore transmission line effects up to a few GHz. So all I said still stands. You are trying to make this an RF discussion, but it is not - I merely used my RF background to illustrate that I do actually have some knowledge when I talk about simulations and their merits.

Also: We do actually use ADS/Momentum to teach students in I think their 4th year here. With these tools being so accessible and common-place now, and frequencies going up in the industry, more and more companies are asking for students with better understanding of the simulation workflow.

[T3sl4co1l]

I enjoyed the implication that one cannot learn anything about a system by poking at it blindly.

Tim

[exe]

Question: are capacitors with reverse geometry any better for decoupling? I concluded that, unless it helps to minimize track lengths, it doesn't matter. So, it should help if supply pins close to each other, but it is pointless if supply pins are far. But I've never checked this. Any opinions?