Poor linearity of a opamp push-pull buffered

[RawCode]

Hello guys.

I'm designing fon an academic project a modified version of the Picoammeter designed by a forum member(https://www.eevblog.com/forum/projects/picoammeter-design/)
My version consist of the same opamp, in the same configuration, but with a push-pull stage to achieve a better current capability, due to the fact that this circuit have a switchable feedback resistor, to measure different ranges of current and a similar stage driven by a microcontroller which outputs the voltage.

The whole circuit is powered by a +/-15V rail, except for the LMC622 which is powered by a /-5V rail.

If i try to measure a 1Meg resistor(in 1meg range), everything seems ok, but if i try to measure a 10k resisor(in 1k range) the measured current is poorly linear to the voltage.

In red the theoric 10k resistor, in blue the measured current.

Can you help me? Why this happens?

[Benta]

It is very difficult for me to understand why you want to do this -and the way you try to do it...

MOSFETs have significant drain-source leakage currents and will skew your results from the start.

The LMC662 is an excellent low power opamp, your "improvement" turns it into a 1970s LM741.

[RawCode]

I made that modification because in simulation, without a push-pull stage, it couldn't drive a more current demanding load, for example 100mA loads and more.

Do you know why this happens? How I can fix this non linearity?

[Kleinstein]

The first point would be to check if the nonlinear effect in the current generation or the current measurement.

The MOSFET stage is inside the OPs FB loop. So normally the OP should correct most of the nonlinear effects, especially gate leakage.  So the error is surprisingly large. The obvious part is to look at the MOSFET stage on it's own - one may have to use different FETs.

[Marco]

MOSFETs have significant drain-source leakage currents and will skew your results from the start.

Leakage doesn't matter for a pushpull stage, it's outputting as a voltage source. In fact it might need to be biased to "leak" more, biased into AB so it doesn't lose regulation near zero current.

[Neomys Sapiens]

The obvious solution would be to use another OP in the position of X3 and X112 - that should be one to directly give you somewhat more output current. If you really need 100mA, you might have to resort to a precision buffer. Something akin to a LT1010 or LMH6321 or the HA9P5002-9Z come to my mind. But 100mA is an exceptional drive capability requirement for such an instrument output, so you might reconsider if you can reduce it to the output current range of some available OPA. AD8512/13 are rated with +/-70mA, so they should give you 50mA at least. ISL55004, ISL28290, THS4043, and LM7321 are also known for a drive capacity above 50mA.

[Marco]

Can you help me? Why this happens?

Are you using a dynamic signal to test it and then graphing current relative to voltage? If so, how fast is it rising?

[magic]

Looks like a massive error which should be detectable with a DMM test at OUT, VINAMP and ADCIN. See which is wrong.

Maybe it oscillates and everything goes to buggery?

[RawCode]

Thank you so much for the replies.

Probably I should have used in this design one of the buffers Neomys Sapiens suggested, but to be honest I didn't know about their existence so I went to a more classical approach, like a push-pull buffer.

As Kleinstein said, the feedback should remove all the non linearities. That's what is driving me crazy: both "source" and "receiver" (X3 and x112, respectively)are  negative feedback opamps, why would they produce such a non linear plot?

 The plot is produce by the circuit itselft. The output of the "modified picomammeter"(X112 and its push-pull stage) is buffered by a voltage follower and then converted by a LTC2402. Same thing for the voltage generator(X3 to be clear). The plot is generated by the program I wrote for this project. The signal to test a generic resistor is produced by a 12 bit microcontroller's DAC, which produces a step for every bit, something like 3 steps per second. To make a sweep from 0V to 10V, 15/20 minutes are necessary

I noticed that if I test X112's output(the point between the output and the gates) the current in the plot drops by a bit. I have no pictures of this phenomenon, which I'll provide tomorrow morning.

Should I try to make a plot using an oscilloscope in xy mode?

[duak]

While there are better solutions, a quick thing to try is to add a 1k0 resistor between the MOSFET gates and the junction of the 0R5 resistors for each buffer.  The op-amp will then source or sink current up to a level at which the corresponding MOSFET will start to conduct and augment the current.  This covers up some of the deadband (edit: was crossover) or backlash in the buffer's transfer function and may be good enough for DC operation.
 

[magic]

Crossover distortion simply is not (that much of) a thing with DC and certainly doesn't get worse with increasing output loading.

I suppose GBW of the source followers increased with load and they started to self-oscillate. A bypass resistor will fix it, until OP increases loading once more and causes the FETs to turn on again.

[Neomys Sapiens]

Now while I did not spend any thoughts to finding out what is happening in your circuit, a short perusal of my sources does show that where someone intended to boost the output of an OPA, the only examples where it was as simple as cobbling two FETs together were those where linearity was not a concern at all.
Circuits can be found in LT AN-18, LT AN-21, NS AN-272.
But I concede that it would be advisable to fint out the reason fot the behaviour, as my first thought was exactly the same as Kleinsteins' - why is the error so large when the FETs are in the loop?

[magic]

But I concede that it would be advisable to fint out the reason fot the behaviour, as my first thought was exactly the same as Kleinsteins' - why is the error so large when the FETs are in the loop?

This guy gets it

LMC660 has 120dB open loop gain at 1Hz. Even a few volts of random offset introduced by the buffer would be attenuated down to microvolts.

[RawCode]

Hello guys.

I did some tests with my oscilloscope.
First i probed the voltage generator(X3) and, as expected, it generates a nice flat voltage according to the microcontroller's DAC. So i would say that the voltage generator is not the source of the problem.

I also tryed to probe the current ammeter(X112 and its buffer). Well, as somebody said, there is an oscillation! There's an oscillation between the opamp output and the gates of the pushpull, and an oscillation at the output of the push-pull stage too.
I'm using a 10x probe.
Output of the push-pull stage:

Point between the opamp's output and the pushpull's gates:

I also tryed to put a 1k resistor between the opamp's output and the push-pull's output, but there were no improvements, the oscillation was still going.
This is the full current sensing circuit:

So it's a stability problem i presume. Any ideas why this happens?
The opamp is introducing a 180° phase delay since it's an inverting opamp. The push-pull should not introduce any phase delays. So why it oscillates? How can i fix it?

[magic]

It seems you are lucky and it's the opamp oscillating, not the source followers.

No, the opamp has open loop 90° phase lag due to internal compensation, giving 270° lag from the inverting input to the output.
The lag of the output buffer is easy enough to measure - probe both nodes simultaneously on two channels. It's probably close to zero.
You probably have close to 90° lag from the output to the inverting input, though, which completes the 360° necessary for oscillation. This is caused by the feedback resistor and any parasitic capacitance (including the opamp's input pin) present at the input node. You can do the math and see if it matters at 1MHz or simply confirm by a two-channel measurement (beware that adding a probe will further increase capacitance on the input, that's why it's nice to have a 100x probe if you don't want to fork $$$ for an active one).

Solution: increase the feedback capacitor. However, 330pF might already be too large for 1GΩ - you really should have a dedicated capacitor for each feedback resistor. See application hints in the datasheet.

edit
Thanks for the 16 megapixels, I wouldn't quite see the grain on your scope's display otherwise

[Kleinstein]

The MOSFET stage can add a little to the phase shift from delays / capacitive loading from the gates. The fast feedback from the 330 pF capacitor should come directly from the OP and not from after the extra buffer.

It is odd to use so many relays. For small signals CMOS switches can be easier to use (e.g. for the Offset signals). If the signal goes to an ADC anyway, there is no real need to have individual offset trimming. The offset voltage should be a fixed values and other errors from leakage current should be small - especially the little part that changes between ranges. So the minimal differences could be corrected in software.

[magic]

The MOSFET stage can add a little to the phase shift from delays / capacitive loading from the gates. The fast feedback from the 330 pF capacitor should come directly from the OP and not from after the extra buffer.

Fair point. I suppose a CMOS rail to rail opamp like this has open loop output impedance about equal to (Vsupply-Vout)/(Iout+Iquiescent), which could be unpleasantly high.

[Kleinstein]

The output impedance of the modern CMOS OPs is usually not that bad. They often have some of the compensation from the output to get better tolerance to capacitive loads. So the open loop output impedance can be in the 100 Ohms range, which is not too bad.

Some older CMOS OPs like the TLC272 had a problem with high output impedance.


Edit:
The MOSFETs are way to high in capacitance and anyway not suitable for high power linear operation.

[RawCode]

Thanks for all the suggestions, much appreciated
I used so many relays because, in my mind, they introduce less parassites in the circuit than a CMOS switche, but sure, i could use CMOS switches at least for the compesation pots.

Reading the LMC622 datasheet i discovered that loading an opamp's output with a capacitor it may induce instabilities in the opamp. I didn't know that 
probably i should have read the whole datasheet before designing the whole circuit. Shame on me.

Anyway, the datasheet itself says that to drive a very capacitive load it is necessary to put a resistor in series with the output. Initially i put a 330 Ohm resistor in series and i noticed that the peak-to-peak amplitude of the oscillation was reduced by a bit, then i tried 1Kohm and it reduced by another bit, so i tried 1MOhm and now it seems that the oscillation is entirely gone. I noticed that when is selected the MegaOhm range(i.e. the 1MOhm resistor is in the feedback path) there's another oscillation, but is the main's 50Hz. Switching to 1GOhm in the feedback path, this oscillation is a bit wider, so i presume it's just ambient noise picked up by a big resistor(even if i calculated the cutoff frequency with the 330pF @1GOgm and it should be 0.5Hz, so i shouldn't see that oscillation)

1K range:

1M range:


Doing that the non linearity dessappeared. YEAH!
What do think about this solution? Is it fine? Is it doable? Is it dumb?

There is just an offset, fixable with one of the pots shown in a picture in the previous replies.

I would like to ask you another thing, it's a bit off-topic though.

As you can see, i'm measuring a 1MOhm resistor.
In the first part of the plot there's a clean 1MOhm line while the opamp has a 1MOhm resistor in the feedback path. Once it saturates, it switches feedback resitor and it set it to a 1kOhm resistor(i.e the next range). As you can see there are 2 major problems.
The first problem is a conversion problem, i.e. converting the ADC data to a more human readable data. I do that dividing the incoming data depending on the range. For example if the opamp is in the 1MEG RANGE, it divides the converted data by 1000000, when it is in the 1K RANGE it divides by 1000 and so on. But, as you can see, the ranges are non contiguous.
Probably i should make another topic, but if you can help me about this problem i would appreciate it a lot.

The second problem, maybe the most dramatic, is the fact that when measuring a 1MOhm Resistor, the 1K RANGE is VERY noisy.
I mean, the 1MOhm in kinda there, but a 24bit converter over 5V and with a 0.00000029V resolution, should be able to read a (5V/1MOhm = 0,000005A -> 1kOhm*0,000005A =) 0.005V signal withouth problems i think. Considering also that the LTC2402 is a precision ADC, and considering also that 0.005V is far away from the minimum value, i would assume that this noise in not generated by the ADC.
This is a very limiting problem if my circuit cant do a full sweep with reasonalbe noise level of a 1MOhm resistor.
This problem was present even before the fix to the oscillation.
Can you help me? Probably is an opamp issue, but how can i improve this mess?

[Kleinstein]

The target should be no oscillation at all and not making the amplitude of the oscillation small.
The main point here is to have the fast feedback via the capacitor directly from the OP and only the slow part from the resistor through the extra driver. The resistor between the OP and MOSFET gate would than only be an addition, needed if the FETs are so excessively large. It would be a good idea to use smaller MOSFETs, at most something like IRF510 if one really needs currents up to 1 A. However the IRF510 needs quite some voltage - so it is not such a good choice. Just 2 BJTs (e.g. BD139/140) and a parallel resistor would also be a possible option.

For protection of the OP one should also have some 100 K at the OPs inverting input, so that the input could withstand a voltage up to a few 100 V. This resistor would also set the cross over to the capacitor for the higher current ranges.

[dietert1]

Recently i had oscillations in a push/pull complementary mosfet output stage, too. In my case there was no opamp involved, but i was using the pair without gate bias circuit, like in the schematic above. Those are big mosfets (IRF540 and IRF9540) and i saw strong oscillation at about 100 MHz. Each mosfet had a 51R gate resistor.

On the web i found a paper where they tried to understand such oscillations. Final result: The higher the parasitic inductance in the source path is compared to the inductance in the drain path, the higher the noise gain that leads to parasitic oscillation. In my case both FETs were mounted on a heat sink (capacitive coupling to drains) and i solved the problem by connecting a 100 pF capacitor from the heatsink to the complementary output (sources). After that the circuit behaved as expected.

Regards, Dieter

[RawCode]

Thank you guys.
You helped me for my thesis work. Much appreciated.

I'll start another topic about the noise that i mentioned before.
Again, thank you very much.

[KE5FX]

Suggest using a couple of ferrite beads at the MOSFET gates.  Usually a bad idea to hook up MOSFET gates to anything without some form of parasitic suppression.

[Marco]

Why bother with MOSFETs are all? Why ask the opamp to fix the huge deadzone instead of using a nice normal NPN/PNP AB stage ... or if you don't have to build it from components at hand, just buy some LMH6321s or something and be really lazy.

PS. just noticed Analog has a post about switchable Rf TIAs and some of the associated bandwidth problems due to parasitic capacitances.

[Marco]

Why couldn't you do a positive current only TIA like the following concept (not a buildable circuit as is obviously).

The lower resistance legs will take over the current as the higher resistance legs saturate, you measure the output voltages of all the legs and add up the currents for the different ranges instead of switching legs with the standard approach.