Well, I'm finally getting moving on this again. I've almost finished the development system. It has a Zybo Z7-20 and a BeagleBoard X15, dedicated gigabit switch, PSU, HDMI to VGA convertors, two port KVM switch, SATA drive for the X15. Still to install are a pair of switched USB 3.0 hubs and a USB 2.0 hub for initial board programming. And I still don't have the KVM USB ports connected to the boards.
I've started analyzing the signal path. Coming out of the ADC the first thing is the filter to correct for AFE and ADC errors. From there it needs to go to the BW filters. The next stage is distribution to the math and trigger sections before going into main memory.
Basic plan is to create an AWG waveform generator IP block. Once I can feed that to memory, I'll create the calibration filter block to correct for part variations in the AFE and ADC. The BW filters are pretty trivial. I plan to implement 20, 50, 100, 200 and user specified with a choice of best rise time with <3% overshoot and a Gaussian step with no overshoot. Once that is writing to memory on the Zybo then comes the task of writing AWG waveforms for all the trigger modes and implementing the trigger IP blocks. In addition to the normal start trigger, I plan to implement a stop trigger so that the scope will stop data acquisition so one can look at the trace before a fault condition was encountered. This is particularly aimed at embedded debugging work.
After that comes the display and measurement IP blocks. Visual persistence is the only thing that looks difficult. The display will be able to operate in triggered YT, roll and XY with math functions as input to XY mode so that one can measure hysteresis loops without needing an analog integrator. I've only just started on the display requirements, so those are still pretty vague.
The DAQ chain is very standard stuff in seismic processing, so the only mysteries are the particulars of Verilog and the Zynq. I'm giving very serious thought to building a 2nd development system with one or two FPGAs from other vendors for testing the Verilog code for portability.
The availability of high performance ADC eval boards at nominal prices makes a bespoke USB DSO practical if there is a portable set of FPGA IP blocks for the FW framework.
The SATA drive for the X15 is in the lower left under the ethernet switch.