This controller is infested with GPL virus. For me that's reason enough to avoid it like a plague
You don't necessarily need to use the code. I don't know much about the code and I didn't look at it. It only runs on HP pins. HR pins don't have FINEDELAY (not even any output delay), so it's pretty much useless on 7010 or Artix. But reading the discussion is interesting by itself.
And the only "shortcoming" the author seem to have "fixed" is he avoided using hard blocks (phasers) which are built into FPGA exactly for use in memory controllers (as far as I understand these blocks are used for write levelling or DDR3/3L). To me that's not that much of a shortcoming.
The shortcomings are basically two:
First, MIG uses very slow IO FIFOs which actually work as a limiting factor (limits the memory speed to 800Mb/s for -1 and -2 grades and 1066Mb/s for -3, which is 4x speed of the FIFO).
Second is the PHASER design. Reading from the memory is synchronized by strobes transmitted from the DDR chip on DQS lines. The strobes only persist while the data is transmitted. Then the Xilinx's ISERDERS needs few more clocks to put the data through. For this purpose, PHASER maintains a free-running clock which is synchronized with DQS strobes. In the absence of reads for some span of time (1 us precisely) they desynchronize. Therefore, MIG has to switch to reading at least once every 1 us. Not a big deal if you constantly read and write, but if you want to write in big blocks (such as when acquiring data from an ADC), these mandatory reads force the controller to switch the direction twice every microsecond, which will take at least 10% off of your write speed.
You don't need MIG to access DDR3 that is connected to Zynq's PS side (which is how vast majority of Zynq-based systems built). Hard DDR controller that is built into PS supports up to 1066 MT/s via 16 or 32bit bus in all speed grades, and if you want to achieve that kind of performance using Artix fabric, you'll need very expensive -3 speed grade.
I don't know the details of Zynq construction, but PS side needs memory for its own purposes. If you want to use substantially all memory bandwidth, I would guess you have to have DDR3 memory on the PL side. But I may be wrong about this.