So there are three schemes described in this appnote: figure 27, 28a and 28b.
They admit that 28a has a problem with increased noise and 28b may be difficult to fabricate accurately at high "reduction ratio".
Figure 27 could in theory be implemented sneakily in lateral PNP input stages, by increasing parasitic collection by the substrate (which normally is undesirable and efforts are made to prevent it), so you could look at a die and never know that a deliberately introduced, significant substrate collector is there.
But the figure 28 schemes are impossible to realize without additional surface collectors and metal traces hooking them up to the mirror and/or ground. So if a chip exists which uses an "advanced" scheme, we could find it, tear it down and see it. So far I haven't seen anything like that. Not in several 358s, not in the RC4558 from Zeptobars and in Chinese RC4558, not in NJM2068 (a Japanese 4558 on steroids), not in the numerous voltage references posted in "metrology". Nor in this LF155 or TL072, for that matter. If these schemes are used, they probably aren't that very common.
This leaves us with the figure 27 scheme, which is hard to disprove by eyeballing because of the aforementioned possibility of a hidden substrate collector. But we can look at its noise implications. Protest if you think I'm wrong, but I'm quite convinced that noise performance of such input stage is simply equivalent to a normal stage running on n-times reduced bias. I will ignore mirror contribution (imagine that it's sufficiently degenerated or whatever) and look at the LTP.
If I got my math right, transconductance of a mirror loaded LTP equals transconductance of each individual transistor. Noise of an undegenerated BJT happens to be equivalent to the Johnson noise of half its intrinsic emitter resistance (which doesn't have real Johnson noise, obviously), and therefore noise of an LTP conveniently equals the "Johnson" noise of 1/gm. And 1/gm happens to be the reactance of Cc at unity gain frequency, so our math is surprisingly easy.
Take a normal 741 with Cc=25~30pF and GBW=1MHz. That's some 5.5~6kΩ impedance and therefore a hair under 10nV/rtHz LTP noise. Multiply by 1.4 because of the NPN emitter followers and we are at 14nV/rtHz. A real 741 has a hair over 20nV/rtHz IIRC.
Now take the "improved" 741 with 5pF. That's 32kΩ and 22nV/rtHz, even before the 1.4x factor. It simply cannot meet the original spec.
Curiously, Raytheon specifies RC1458 noise similarly to 741, but Motorola's MC1458 density plot shows 40nV/rtHz. Hmm... that puppy may need a teardown.