Snubbers can be great in reducing the noise at its very source. In some cases, you can do without snubbers. Sometimes, you'll need a small one to prevent your MOSFETs from blowing from voltage spikes. Even a very small one, with practically no power loss, can do wonders. Sometimes, you can go quite far in reducing EMI, if you don't mind the efficiency loss.
There are also places where you
can't. It would be nice to add some supply inductance to those "integrated switch" chips (synchronous or otherwise), but sadly as they draw VCC from the same node, you don't have much choice but to follow the same tired advice upon which those chips were designed... "minimize inductance".
On the upside, they're usually compact enough that this is okay, but -- they keep getting faster and faster, too, making their own problems worse.
(I may state the obvious, but for me, it took time to understand what a snubber IS, there's a lot of false information. It has absolutely nothing to do with: switching (rise/fall) time, switch losses, switching frequency, inductor inductance / spikes... It really is there to dampen the energy circulating in the parasitic inductances in layout and capacitors, which is happening much beyond switching frequency and independend of it (typically at something like 30 - 500 MHz)).
That's not true; snubbers serve all three purposes. Much increase in rise/fall time is usually avoided, but you'll still see it on large IGBTs where the switching speed is low anyway (e.g., large VFDs).
Voltage/current peak clamping networks fall under the domain of snubbers. Often, all three are effectively combined, for example using a dV/dt snubber on a flyback supply to increase risetime (giving the transistor more time to turn off, reducing turn-off losses), clamp the peak overshoot (due to leakage inductance), and dampen ringing (due to both LL and Lp).
You may need to add a snubber over both switches (diode and MOSFET), so one between GND and switch node and another between V+ and switch node.
Yup. The general idea is to dampen the stray inductance (or snubber inductance, if you're tuning it to the application). Which, if you don't know where it's concentrated (or you know, and it's distributed, so it's impossible to dampen the full thing at any one point), one across each device is necessary.
Boost converters have the problem of diode reverse recovery, causing "unlimited" short circuit currents, and a huge EMI spike when the short circuit suddenly disappers. Snubber helps over the diode, but what you really need is a diode which is specified as both ultra mega giga fast reverse recovery AND soft reverse recovery (snubber may still be beneficial.)
If you can't avoid the recovery (and sometimes, even schottky diodes are bad -- because their sharp C(V) curve ends up looking an awful lot like reverse recovery, anyway!), you need to add loop inductance (which reduces dI/dt, recovery charge and peak recovery current). Which, in turn, has to be snubbed. You can avoid some if you use a saturable reactor (old school!), which simply adds some delay between switching and recovery without storing too much energy.
Also works for interference type synchronous switches, which is good for bidirectional conduction where you can't tolerate a body diode being accidentally forward biased for 10 nanoseconds (and maybe bringing snap recovery with it!).
You can find instructions how to properly size the snubber components by experimenting with the circuit. I have found that the best way is just to try out different values until you reach the optimum point.
I have quite good luck estimating inductance by layout, and sizing the RLCs according to that. Design equations: C = 2 to 5 times Cjo, R = sqrt(L/C). Cjo being the average capacitance of whatever junction is open at the time / what the R+C is connected across. For a dV/dt snubber, these values should still be typical, but the L may be a different value (e.g., Lp instead of LL). For a peak clamp, use much larger C (enough to charge by perhaps 10% of total supply?), and R = Tcyc / (10*C) (i.e., a few R*C time constants to allow the capacitor to mostly discharge during the idle period).
Fine tuning is done by adjusting R and C up and down by 1.5-2x per step; not usually worth getting any more particular than that. A good approach is to use an overly large capacitor and find the correct damping, then drop C until it just starts getting worse, then fine tuning the resistor one last time. You'll usually be left with some overshoot (going for a rock solid edge usually costs too much dissipation, but can be done).
In situations where two inductances are at work (like the flyback example), you can use two R+Cs, to dampen LL and Lp seperately. If not using a dV/dt or other snubber, of course.
Tim
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